mirror of
https://sourceware.org/git/binutils-gdb.git
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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
709 lines
21 KiB
C
709 lines
21 KiB
C
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
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/* Disassembler interface for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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- the resultant file is machine generated, cgen-dis.in isn't
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "disassemble.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "libiberty.h"
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#include "m32r-desc.h"
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#include "m32r-opc.h"
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#include "opintl.h"
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/* Default text to print if an instruction isn't recognized. */
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#define UNKNOWN_INSN_MSG _("*unknown*")
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static void print_normal
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(CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
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static void print_address
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(CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
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static void print_keyword
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(CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
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static void print_insn_normal
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(CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
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static int print_insn
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned);
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static int default_print_insn
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
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static int read_insn
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(CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
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unsigned long *);
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/* -- disassembler routines inserted here. */
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/* -- dis.c */
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/* Print signed operands with '#' prefixes. */
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static void
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print_signed_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "#");
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(*info->fprintf_func) (info->stream, "%ld", value);
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}
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/* Print unsigned operands with '#' prefixes. */
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static void
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print_unsigned_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "#");
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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}
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/* Handle '#' prefixes as operands. */
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static void
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print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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long value ATTRIBUTE_UNUSED,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, "#");
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}
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#undef CGEN_PRINT_INSN
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#define CGEN_PRINT_INSN my_print_insn
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static int
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my_print_insn (CGEN_CPU_DESC cd,
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bfd_vma pc,
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disassemble_info *info)
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{
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bfd_byte buffer[CGEN_MAX_INSN_SIZE];
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bfd_byte *buf = buffer;
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int status;
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int buflen = (pc & 3) == 0 ? 4 : 2;
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int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
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bfd_byte *x;
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/* Read the base part of the insn. */
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status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
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buf, buflen, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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/* 32 bit insn? */
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x = (big_p ? &buf[0] : &buf[3]);
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if ((pc & 3) == 0 && (*x & 0x80) != 0)
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return print_insn (cd, pc, info, buf, buflen);
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/* Print the first insn. */
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if ((pc & 3) == 0)
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{
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buf += (big_p ? 0 : 2);
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if (print_insn (cd, pc, info, buf, 2) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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buf += (big_p ? 2 : -2);
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}
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x = (big_p ? &buf[0] : &buf[1]);
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if (*x & 0x80)
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{
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/* Parallel. */
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(*info->fprintf_func) (info->stream, " || ");
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*x &= 0x7f;
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}
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else
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(*info->fprintf_func) (info->stream, " -> ");
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/* The "& 3" is to pass a consistent address.
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Parallel insns arguably both begin on the word boundary.
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Also, branch insns are calculated relative to the word boundary. */
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if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
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(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
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return (pc & 3) ? 2 : 4;
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}
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/* -- */
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void m32r_cgen_print_operand
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(CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
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/* Main entry point for printing operands.
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XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
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of dis-asm.h on cgen.h.
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This function is basically just a big switch statement. Earlier versions
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used tables to look up the function to use, but
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- if the table contains both assembler and disassembler functions then
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the disassembler contains much of the assembler and vice-versa,
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- there's a lot of inlining possibilities as things grow,
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- using a switch statement avoids the function call overhead.
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This function could be moved into `print_insn_normal', but keeping it
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separate makes clear the interface between `print_insn_normal' and each of
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the handlers. */
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void
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m32r_cgen_print_operand (CGEN_CPU_DESC cd,
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int opindex,
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void * xinfo,
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CGEN_FIELDS *fields,
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void const *attrs ATTRIBUTE_UNUSED,
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bfd_vma pc,
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int length)
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{
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disassemble_info *info = (disassemble_info *) xinfo;
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switch (opindex)
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{
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case M32R_OPERAND_ACC :
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print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
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break;
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case M32R_OPERAND_ACCD :
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print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
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break;
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case M32R_OPERAND_ACCS :
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print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
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break;
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case M32R_OPERAND_DCR :
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print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
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break;
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case M32R_OPERAND_DISP16 :
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print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP24 :
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print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DISP8 :
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print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
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break;
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case M32R_OPERAND_DR :
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print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
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break;
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case M32R_OPERAND_HASH :
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print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
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break;
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case M32R_OPERAND_HI16 :
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print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
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break;
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case M32R_OPERAND_IMM1 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_imm1, 0, pc, length);
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break;
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case M32R_OPERAND_SCR :
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print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
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break;
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case M32R_OPERAND_SIMM16 :
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print_signed_with_hash_prefix (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
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break;
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case M32R_OPERAND_SIMM8 :
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print_signed_with_hash_prefix (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
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break;
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case M32R_OPERAND_SLO16 :
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print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
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break;
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case M32R_OPERAND_SR :
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print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
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break;
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case M32R_OPERAND_SRC1 :
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print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
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break;
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case M32R_OPERAND_SRC2 :
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print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
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break;
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case M32R_OPERAND_UIMM16 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_uimm16, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM24 :
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print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
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break;
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case M32R_OPERAND_UIMM3 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_uimm3, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM4 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_uimm4, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM5 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_uimm5, 0, pc, length);
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break;
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case M32R_OPERAND_UIMM8 :
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print_unsigned_with_hash_prefix (cd, info, fields->f_uimm8, 0, pc, length);
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break;
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case M32R_OPERAND_ULO16 :
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print_normal (cd, info, fields->f_uimm16, 0, pc, length);
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break;
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default :
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/* xgettext:c-format */
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opcodes_error_handler
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(_("internal error: unrecognized field %d while printing insn"),
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opindex);
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abort ();
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}
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}
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cgen_print_fn * const m32r_cgen_print_handlers[] =
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{
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print_insn_normal,
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};
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void
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m32r_cgen_init_dis (CGEN_CPU_DESC cd)
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{
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m32r_cgen_init_opcode_table (cd);
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m32r_cgen_init_ibld_table (cd);
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cd->print_handlers = & m32r_cgen_print_handlers[0];
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cd->print_operand = m32r_cgen_print_operand;
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}
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/* Default print handler. */
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static void
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print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void *dis_info,
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long value,
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unsigned int attrs,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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/* Print the operand as directed by the attributes. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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; /* nothing to do */
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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(*info->fprintf_func) (info->stream, "%ld", value);
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else
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(*info->fprintf_func) (info->stream, "0x%lx", value);
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}
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/* Default address handler. */
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static void
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print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void *dis_info,
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bfd_vma value,
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unsigned int attrs,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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/* Print the operand as directed by the attributes. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
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; /* Nothing to do. */
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
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(*info->print_address_func) (value, info);
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
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(*info->print_address_func) (value, info);
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else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
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(*info->fprintf_func) (info->stream, "%ld", (long) value);
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else
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(*info->fprintf_func) (info->stream, "0x%lx", (long) value);
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}
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/* Keyword print handler. */
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static void
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print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void *dis_info,
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CGEN_KEYWORD *keyword_table,
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long value,
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unsigned int attrs ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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const CGEN_KEYWORD_ENTRY *ke;
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ke = cgen_keyword_lookup_value (keyword_table, value);
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if (ke != NULL)
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(*info->fprintf_func) (info->stream, "%s", ke->name);
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else
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(*info->fprintf_func) (info->stream, "???");
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}
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/* Default insn printer.
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DIS_INFO is defined as `void *' so the disassembler needn't know anything
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about disassemble_info. */
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static void
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print_insn_normal (CGEN_CPU_DESC cd,
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void *dis_info,
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const CGEN_INSN *insn,
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CGEN_FIELDS *fields,
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bfd_vma pc,
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int length)
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{
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const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
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disassemble_info *info = (disassemble_info *) dis_info;
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const CGEN_SYNTAX_CHAR_TYPE *syn;
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CGEN_INIT_PRINT (cd);
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for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
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{
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if (CGEN_SYNTAX_MNEMONIC_P (*syn))
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{
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(*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
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continue;
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}
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if (CGEN_SYNTAX_CHAR_P (*syn))
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{
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(*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
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continue;
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}
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/* We have an operand. */
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m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
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fields, CGEN_INSN_ATTRS (insn), pc, length);
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}
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}
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/* Subroutine of print_insn. Reads an insn into the given buffers and updates
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the extract info.
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Returns 0 if all is well, non-zero otherwise. */
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static int
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read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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bfd_vma pc,
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disassemble_info *info,
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bfd_byte *buf,
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int buflen,
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CGEN_EXTRACT_INFO *ex_info,
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unsigned long *insn_value)
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{
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int status = (*info->read_memory_func) (pc, buf, buflen, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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ex_info->dis_info = info;
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ex_info->valid = (1 << buflen) - 1;
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ex_info->insn_bytes = buf;
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*insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
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return 0;
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}
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/* Utility to print an insn.
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BUF is the base part of the insn, target byte order, BUFLEN bytes long.
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The result is the size of the insn in bytes or zero for an unknown insn
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or -1 if an error occurs fetching data (memory_error_func will have
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been called). */
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static int
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print_insn (CGEN_CPU_DESC cd,
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bfd_vma pc,
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disassemble_info *info,
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bfd_byte *buf,
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unsigned int buflen)
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{
|
||
CGEN_INSN_INT insn_value;
|
||
const CGEN_INSN_LIST *insn_list;
|
||
CGEN_EXTRACT_INFO ex_info;
|
||
int basesize;
|
||
|
||
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
|
||
basesize = cd->base_insn_bitsize < buflen * 8 ?
|
||
cd->base_insn_bitsize : buflen * 8;
|
||
insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
|
||
|
||
|
||
/* Fill in ex_info fields like read_insn would. Don't actually call
|
||
read_insn, since the incoming buffer is already read (and possibly
|
||
modified a la m32r). */
|
||
ex_info.valid = (1 << buflen) - 1;
|
||
ex_info.dis_info = info;
|
||
ex_info.insn_bytes = buf;
|
||
|
||
/* The instructions are stored in hash lists.
|
||
Pick the first one and keep trying until we find the right one. */
|
||
|
||
insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
|
||
while (insn_list != NULL)
|
||
{
|
||
const CGEN_INSN *insn = insn_list->insn;
|
||
CGEN_FIELDS fields;
|
||
int length;
|
||
unsigned long insn_value_cropped;
|
||
|
||
#ifdef CGEN_VALIDATE_INSN_SUPPORTED
|
||
/* Not needed as insn shouldn't be in hash lists if not supported. */
|
||
/* Supported by this cpu? */
|
||
if (! m32r_cgen_insn_supported (cd, insn))
|
||
{
|
||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||
continue;
|
||
}
|
||
#endif
|
||
|
||
/* Basic bit mask must be correct. */
|
||
/* ??? May wish to allow target to defer this check until the extract
|
||
handler. */
|
||
|
||
/* Base size may exceed this instruction's size. Extract the
|
||
relevant part from the buffer. */
|
||
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
|
||
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
|
||
insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
|
||
info->endian == BFD_ENDIAN_BIG);
|
||
else
|
||
insn_value_cropped = insn_value;
|
||
|
||
if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
|
||
== CGEN_INSN_BASE_VALUE (insn))
|
||
{
|
||
/* Printing is handled in two passes. The first pass parses the
|
||
machine insn and extracts the fields. The second pass prints
|
||
them. */
|
||
|
||
/* Make sure the entire insn is loaded into insn_value, if it
|
||
can fit. */
|
||
if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
|
||
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
|
||
{
|
||
unsigned long full_insn_value;
|
||
int rc = read_insn (cd, pc, info, buf,
|
||
CGEN_INSN_BITSIZE (insn) / 8,
|
||
& ex_info, & full_insn_value);
|
||
if (rc != 0)
|
||
return rc;
|
||
length = CGEN_EXTRACT_FN (cd, insn)
|
||
(cd, insn, &ex_info, full_insn_value, &fields, pc);
|
||
}
|
||
else
|
||
length = CGEN_EXTRACT_FN (cd, insn)
|
||
(cd, insn, &ex_info, insn_value_cropped, &fields, pc);
|
||
|
||
/* Length < 0 -> error. */
|
||
if (length < 0)
|
||
return length;
|
||
if (length > 0)
|
||
{
|
||
CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
|
||
/* Length is in bits, result is in bytes. */
|
||
return length / 8;
|
||
}
|
||
}
|
||
|
||
insn_list = CGEN_DIS_NEXT_INSN (insn_list);
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
/* Default value for CGEN_PRINT_INSN.
|
||
The result is the size of the insn in bytes or zero for an unknown insn
|
||
or -1 if an error occured fetching bytes. */
|
||
|
||
#ifndef CGEN_PRINT_INSN
|
||
#define CGEN_PRINT_INSN default_print_insn
|
||
#endif
|
||
|
||
static int
|
||
default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||
{
|
||
bfd_byte buf[CGEN_MAX_INSN_SIZE];
|
||
int buflen;
|
||
int status;
|
||
|
||
/* Attempt to read the base part of the insn. */
|
||
buflen = cd->base_insn_bitsize / 8;
|
||
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||
|
||
/* Try again with the minimum part, if min < base. */
|
||
if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
|
||
{
|
||
buflen = cd->min_insn_bitsize / 8;
|
||
status = (*info->read_memory_func) (pc, buf, buflen, info);
|
||
}
|
||
|
||
if (status != 0)
|
||
{
|
||
(*info->memory_error_func) (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
return print_insn (cd, pc, info, buf, buflen);
|
||
}
|
||
|
||
/* Main entry point.
|
||
Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction (in bytes). */
|
||
|
||
typedef struct cpu_desc_list
|
||
{
|
||
struct cpu_desc_list *next;
|
||
CGEN_BITSET *isa;
|
||
int mach;
|
||
int endian;
|
||
int insn_endian;
|
||
CGEN_CPU_DESC cd;
|
||
} cpu_desc_list;
|
||
|
||
int
|
||
print_insn_m32r (bfd_vma pc, disassemble_info *info)
|
||
{
|
||
static cpu_desc_list *cd_list = 0;
|
||
cpu_desc_list *cl = 0;
|
||
static CGEN_CPU_DESC cd = 0;
|
||
static CGEN_BITSET *prev_isa;
|
||
static int prev_mach;
|
||
static int prev_endian;
|
||
static int prev_insn_endian;
|
||
int length;
|
||
CGEN_BITSET *isa;
|
||
int mach;
|
||
int endian = (info->endian == BFD_ENDIAN_BIG
|
||
? CGEN_ENDIAN_BIG
|
||
: CGEN_ENDIAN_LITTLE);
|
||
int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
|
||
? CGEN_ENDIAN_BIG
|
||
: CGEN_ENDIAN_LITTLE);
|
||
enum bfd_architecture arch;
|
||
|
||
/* ??? gdb will set mach but leave the architecture as "unknown" */
|
||
#ifndef CGEN_BFD_ARCH
|
||
#define CGEN_BFD_ARCH bfd_arch_m32r
|
||
#endif
|
||
arch = info->arch;
|
||
if (arch == bfd_arch_unknown)
|
||
arch = CGEN_BFD_ARCH;
|
||
|
||
/* There's no standard way to compute the machine or isa number
|
||
so we leave it to the target. */
|
||
#ifdef CGEN_COMPUTE_MACH
|
||
mach = CGEN_COMPUTE_MACH (info);
|
||
#else
|
||
mach = info->mach;
|
||
#endif
|
||
|
||
#ifdef CGEN_COMPUTE_ISA
|
||
{
|
||
static CGEN_BITSET *permanent_isa;
|
||
|
||
if (!permanent_isa)
|
||
permanent_isa = cgen_bitset_create (MAX_ISAS);
|
||
isa = permanent_isa;
|
||
cgen_bitset_clear (isa);
|
||
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
|
||
}
|
||
#else
|
||
isa = info->private_data;
|
||
#endif
|
||
|
||
/* If we've switched cpu's, try to find a handle we've used before */
|
||
if (cd
|
||
&& (cgen_bitset_compare (isa, prev_isa) != 0
|
||
|| mach != prev_mach
|
||
|| endian != prev_endian))
|
||
{
|
||
cd = 0;
|
||
for (cl = cd_list; cl; cl = cl->next)
|
||
{
|
||
if (cgen_bitset_compare (cl->isa, isa) == 0 &&
|
||
cl->mach == mach &&
|
||
cl->endian == endian)
|
||
{
|
||
cd = cl->cd;
|
||
prev_isa = cd->isas;
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
|
||
/* If we haven't initialized yet, initialize the opcode table. */
|
||
if (! cd)
|
||
{
|
||
const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
|
||
const char *mach_name;
|
||
|
||
if (!arch_type)
|
||
abort ();
|
||
mach_name = arch_type->printable_name;
|
||
|
||
prev_isa = cgen_bitset_copy (isa);
|
||
prev_mach = mach;
|
||
prev_endian = endian;
|
||
prev_insn_endian = insn_endian;
|
||
cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
|
||
CGEN_CPU_OPEN_BFDMACH, mach_name,
|
||
CGEN_CPU_OPEN_ENDIAN, prev_endian,
|
||
CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
|
||
CGEN_CPU_OPEN_END);
|
||
if (!cd)
|
||
abort ();
|
||
|
||
/* Save this away for future reference. */
|
||
cl = xmalloc (sizeof (struct cpu_desc_list));
|
||
cl->cd = cd;
|
||
cl->isa = prev_isa;
|
||
cl->mach = mach;
|
||
cl->endian = endian;
|
||
cl->next = cd_list;
|
||
cd_list = cl;
|
||
|
||
m32r_cgen_init_dis (cd);
|
||
}
|
||
|
||
/* We try to have as much common code as possible.
|
||
But at this point some targets need to take over. */
|
||
/* ??? Some targets may need a hook elsewhere. Try to avoid this,
|
||
but if not possible try to move this hook elsewhere rather than
|
||
have two hooks. */
|
||
length = CGEN_PRINT_INSN (cd, pc, info);
|
||
if (length > 0)
|
||
return length;
|
||
if (length < 0)
|
||
return -1;
|
||
|
||
(*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
|
||
return cd->default_insn_bitsize / 8;
|
||
}
|