mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-27 04:52:05 +08:00
293 lines
9.2 KiB
Plaintext
293 lines
9.2 KiB
Plaintext
@c Copyright (C) 1997 Free Software Foundation, Inc.
|
|
@c This is part of the GAS manual.
|
|
@c For copying conditions, see the file as.texinfo.
|
|
@ifset GENERIC
|
|
@page
|
|
@node D30V-Dependent
|
|
@chapter D30V Dependent Features
|
|
@end ifset
|
|
@ifclear GENERIC
|
|
@node Machine Dependencies
|
|
@chapter D30V Dependent Features
|
|
@end ifclear
|
|
|
|
@cindex D30V support
|
|
@menu
|
|
* D30V-Opts:: D30V Options
|
|
* D30V-Syntax:: Syntax
|
|
* D30V-Float:: Floating Point
|
|
* D30V-Opcodes:: Opcodes
|
|
@end menu
|
|
|
|
@node D30V-Opts
|
|
@section D30V Options
|
|
@cindex options, D30V
|
|
@cindex D30V options
|
|
The Mitsubishi D30V version of @code{@value{AS}} has a few machine
|
|
dependent options.
|
|
|
|
@table @samp
|
|
@item -O
|
|
The D30V can often execute two sub-instructions in parallel. When this option
|
|
is used, @code{@value{AS}} will attempt to optimize its output by detecting when
|
|
instructions can be executed in parallel.
|
|
|
|
@item -n
|
|
When this option is used, @code{@value{AS}} will issue a warning every
|
|
time it adds a nop instruction.
|
|
|
|
@item -N
|
|
When this option is used, @code{@value{AS}} will issue a warning if it
|
|
needs to insert a nop after a 32-bit multiply before a load or 16-bit
|
|
multiply instruction.
|
|
@end table
|
|
|
|
@node D30V-Syntax
|
|
@section Syntax
|
|
@cindex D30V syntax
|
|
@cindex syntax, D30V
|
|
|
|
The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual.
|
|
The differences are detailed below.
|
|
|
|
@menu
|
|
* D30V-Size:: Size Modifiers
|
|
* D30V-Subs:: Sub-Instructions
|
|
* D30V-Chars:: Special Characters
|
|
* D30V-Guarded:: Guarded Execution
|
|
* D30V-Regs:: Register Names
|
|
* D30V-Addressing:: Addressing Modes
|
|
@end menu
|
|
|
|
|
|
@node D30V-Size
|
|
@subsection Size Modifiers
|
|
@cindex D30V size modifiers
|
|
@cindex size modifiers, D30V
|
|
The D30V version of @code{@value{AS}} uses the instruction names in the D30V
|
|
Architecture Manual. However, the names in the manual are sometimes ambiguous.
|
|
There are instruction names that can assemble to a short or long form opcode.
|
|
How does the assembler pick the correct form? @code{@value{AS}} will always pick the
|
|
smallest form if it can. When dealing with a symbol that is not defined yet when a
|
|
line is being assembled, it will always use the long form. If you need to force the
|
|
assembler to use either the short or long form of the instruction, you can append
|
|
either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
|
|
an assembly program and you want to do a branch to a symbol that is defined later
|
|
in your program, you can write @samp{bra.s foo}.
|
|
Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
|
|
have both short and long forms.
|
|
|
|
@node D30V-Subs
|
|
@subsection Sub-Instructions
|
|
@cindex D30V sub-instructions
|
|
@cindex sub-instructions, D30V
|
|
The D30V assembler takes as input a series of instructions, either one-per-line,
|
|
or in the special two-per-line format described in the next section. Some of these
|
|
instructions will be short-form or sub-instructions. These sub-instructions can be packed
|
|
into a single instruction. The assembler will do this automatically. It will also detect
|
|
when it should not pack instructions. For example, when a label is defined, the next
|
|
instruction will never be packaged with the previous one. Whenever a branch and link
|
|
instruction is called, it will not be packaged with the next instruction so the return
|
|
address will be valid. Nops are automatically inserted when necessary.
|
|
|
|
If you do not want the assembler automatically making these decisions, you can control
|
|
the packaging and execution type (parallel or sequential) with the special execution
|
|
symbols described in the next section.
|
|
|
|
@node D30V-Chars
|
|
@subsection Special Characters
|
|
@cindex line comment character, D30V
|
|
@cindex D30V line comment character
|
|
@samp{;} and @samp{#} are the line comment characters.
|
|
@cindex sub-instruction ordering, D30V
|
|
@cindex D30V sub-instruction ordering
|
|
Sub-instructions may be executed in order, in reverse-order, or in parallel.
|
|
Instructions listed in the standard one-per-line format will be executed
|
|
sequentially unless you use the @samp{-O} option.
|
|
|
|
To specify the executing order, use the following symbols:
|
|
@table @samp
|
|
@item ->
|
|
Sequential with instruction on the left first.
|
|
|
|
@item <-
|
|
Sequential with instruction on the right first.
|
|
|
|
@item ||
|
|
Parallel
|
|
@end table
|
|
|
|
The D30V syntax allows either one instruction per line, one instruction per line with
|
|
the execution symbol, or two instructions per line. For example
|
|
@table @code
|
|
@item abs r2,r3 -> abs r4,r5
|
|
Execute these sequentially. The instruction on the right is in the right
|
|
container and is executed second.
|
|
|
|
@item abs r2,r3 <- abs r4,r5
|
|
Execute these reverse-sequentially. The instruction on the right is in the right
|
|
container, and is executed first.
|
|
|
|
@item abs r2,r3 || abs r4,r5
|
|
Execute these in parallel.
|
|
|
|
@item ldw r2,@@(r3,r4) ||
|
|
@itemx mulx r6,r8,r9
|
|
Two-line format. Execute these in parallel.
|
|
|
|
@item mulx a0,r8,r9
|
|
@itemx stw r2,@@(r3,r4)
|
|
Two-line format. Execute these sequentially unless @samp{-O} option is
|
|
used. If the @samp{-O} option is used, the assembler will determine if
|
|
the instructions could be done in parallel (the above two instructions
|
|
can be done in parallel), and if so, emit them as parallel instructions.
|
|
The assembler will put them in the proper containers. In the above
|
|
example, the assembler will put the @samp{stw} instruction in left
|
|
container and the @samp{mulx} instruction in the right container.
|
|
|
|
@item stw r2,@@(r3,r4) ->
|
|
@itemx mulx a0,r8,r9
|
|
Two-line format. Execute the @samp{stw} instruction followed by the
|
|
@samp{mulx} instruction sequentially. The first instruction goes in the
|
|
left container and the second instruction goes into right container.
|
|
The assembler will give an error if the machine ordering constraints are
|
|
violated.
|
|
|
|
@item stw r2,@@(r3,r4) <-
|
|
@itemx mulx a0,r8,r9
|
|
Same as previous example, except that the @samp{mulx} instruction is
|
|
executed before the @samp{stw} instruction.
|
|
@end table
|
|
|
|
@cindex symbol names, @samp{$} in
|
|
@cindex @code{$} in symbol names
|
|
Since @samp{$} has no special meaning, you may use it in symbol names.
|
|
|
|
@node D30V-Guarded
|
|
@subsection Guarded Execution
|
|
@cindex D30V Guarded Execution
|
|
@code{@value{AS}} supports the full range of guarded execution
|
|
directives for each instruction. Just append the directive after the
|
|
instruction proper. The directives are:
|
|
|
|
@table @samp
|
|
@item /tx
|
|
Execute the instruction if flag f0 is true.
|
|
@item /fx
|
|
Execute the instruction if flag f0 is false.
|
|
@item /xt
|
|
Execute the instruction if flag f1 is true.
|
|
@item /xf
|
|
Execute the instruction if flag f1 is false.
|
|
@item /tt
|
|
Execute the instruction if both flags f0 and f1 are true.
|
|
@item /tf
|
|
Execute the instruction if flag f0 is true and flag f1 is false.
|
|
@end table
|
|
|
|
@node D30V-Regs
|
|
@subsection Register Names
|
|
@cindex D30V registers
|
|
@cindex registers, D30V
|
|
You can use the predefined symbols @samp{r0} through @samp{r63} to refer
|
|
to the D30V registers. You can also use @samp{sp} as an alias for
|
|
@samp{r63} and @samp{link} as an alias for @samp{r62}. The accumulators
|
|
are @samp{a0} and @samp{a1}.
|
|
|
|
The D30V also has predefined symbols for these control registers and status bits:
|
|
@table @code
|
|
@item psw
|
|
Processor Status Word
|
|
@item bpsw
|
|
Backup Processor Status Word
|
|
@item pc
|
|
Program Counter
|
|
@item bpc
|
|
Backup Program Counter
|
|
@item rpt_c
|
|
Repeat Count
|
|
@item rpt_s
|
|
Repeat Start address
|
|
@item rpt_e
|
|
Repeat End address
|
|
@item mod_s
|
|
Modulo Start address
|
|
@item mod_e
|
|
Modulo End address
|
|
@item iba
|
|
Instruction Break Address
|
|
@item f0
|
|
Flag 0
|
|
@item f1
|
|
Flag 1
|
|
@item f2
|
|
Flag 2
|
|
@item f3
|
|
Flag 3
|
|
@item f4
|
|
Flag 4
|
|
@item f5
|
|
Flag 5
|
|
@item f6
|
|
Flag 6
|
|
@item f7
|
|
Flag 7
|
|
@item s
|
|
Same as flag 4 (saturation flag)
|
|
@item v
|
|
Same as flag 5 (overflow flag)
|
|
@item va
|
|
Same as flag 6 (sticky overflow flag)
|
|
@item c
|
|
Same as flag 7 (carry/borrow flag)
|
|
@item b
|
|
Same as flag 7 (carry/borrow flag)
|
|
@end table
|
|
|
|
@node D30V-Addressing
|
|
@subsection Addressing Modes
|
|
@cindex addressing modes, D30V
|
|
@cindex D30V addressing modes
|
|
@code{@value{AS}} understands the following addressing modes for the D30V.
|
|
@code{R@var{n}} in the following refers to any of the numbered
|
|
registers, but @emph{not} the control registers.
|
|
@table @code
|
|
@item R@var{n}
|
|
Register direct
|
|
@item @@R@var{n}
|
|
Register indirect
|
|
@item @@R@var{n}+
|
|
Register indirect with post-increment
|
|
@item @@R@var{n}-
|
|
Register indirect with post-decrement
|
|
@item @@-SP
|
|
Register indirect with pre-decrement
|
|
@item @@(@var{disp}, R@var{n})
|
|
Register indirect with displacement
|
|
@item @var{addr}
|
|
PC relative address (for branch or rep).
|
|
@item #@var{imm}
|
|
Immediate data (the @samp{#} is optional and ignored)
|
|
@end table
|
|
|
|
@node D30V-Float
|
|
@section Floating Point
|
|
@cindex floating point, D30V
|
|
@cindex D30V floating point
|
|
The D30V has no hardware floating point, but the @code{.float} and @code{.double}
|
|
directives generates @sc{ieee} floating-point numbers for compatibility
|
|
with other development tools.
|
|
|
|
@node D30V-Opcodes
|
|
@section Opcodes
|
|
@cindex D30V opcode summary
|
|
@cindex opcode summary, D30V
|
|
@cindex mnemonics, D30V
|
|
@cindex instruction summary, D30V
|
|
For detailed information on the D30V machine instruction set, see
|
|
@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
|
|
(Mitsubishi Electric Corp.).
|
|
@code{@value{AS}} implements all the standard D30V opcodes. The only changes are those
|
|
described in the section on size modifiers
|
|
|