Richard Sandiford 6327658ee7 aarch64: Add support for +mops ... This patch adds support for FEAT_MOPS, an Armv8.8-A extension that provides memcpy and memset acceleration instructions. I took the perhaps controversial decision to generate the individual instruction forms using macros rather than list them out individually. This becomes useful with a follow-on patch to check that code follows the correct P/M/E sequence. [https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en] include/ * opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro. (AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS. (AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd. (AARCH64_OPND_MOPS_ADDR_Rs): Likewise. (AARCH64_OPND_MOPS_WB_Rn): Likewise. opcodes/ * aarch64-asm.h (ins_x0_to_x30): New inserter. * aarch64-asm.c (aarch64_ins_x0_to_x30): New function. * aarch64-dis.h (ext_x0_to_x30): New extractor. * aarch64-dis.c (aarch64_ext_x0_to_x30): New function. * aarch64-tbl.h (aarch64_feature_mops): New feature set. (aarch64_feature_mops_memtag): Likewise. (MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN) (MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN) (MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN) (MOPS_SET_INSN): New macros. (aarch64_opcode_table): Add MOPS instructions. (aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (verify_three_different_regs): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * doc/c-aarch64.texi: Document +mops. * config/tc-aarch64.c (parse_x0_to_x30): New function. (parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn. (aarch64_features): Add "mops". * testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test. * testsuite/gas/aarch64/mops_invalid.s, * testsuite/gas/aarch64/mops_invalid.d, * testsuite/gas/aarch64/mops_invalid.l: Likewise.		2021-12-02 15:00:57 +00:00
..
aarch64.h	aarch64: Add support for +mops	2021-12-02 15:00:57 +00:00
alpha.h
arc-attrs.h
arc-func.h
arc.h	Use bool in include	2021-03-31 10:49:23 +10:30
arm.h	arm: add armv9-a architecture to -march	2021-11-01 10:51:03 +00:00
avr.h
bfin.h
cgen.h	Remove bfd_stdint.h	2021-03-31 10:49:23 +10:30
ChangeLog-0415
ChangeLog-9103
convex.h
cr16.h	Remove strneq macro and use startswith.	2021-04-01 15:00:56 +02:00
cris.h
crx.h
csky.h
d10v.h
d30v.h
dlx.h
ft32.h
h8300.h
hppa.h
i386.h
ia64.h
loongarch.h	LoongArch opcodes support	2021-10-24 21:36:31 +10:30
m68hc11.h
m68k.h
metag.h
mips.h	MIPS/opcodes: Properly handle ISA exclusion	2021-05-29 03:26:32 +02:00
mmix.h
mn10200.h
mn10300.h
moxie.h
msp430-decode.h
msp430.h
nds32.h
nfp.h	Remove bfd_stdint.h	2021-03-31 10:49:23 +10:30
nios2.h
nios2r1.h
nios2r2.h
np1.h
ns32k.h
pdp11.h
pj.h
pn.h
ppc.h	Remove bfd_stdint.h	2021-03-31 10:49:23 +10:30
pru.h
pyr.h
riscv-opc.h	RISC-V: Support rvv extension with released version 1.0.	2021-11-17 20:18:11 +08:00
riscv.h	RISC-V: The vtype immediate with more than the defined 8 bits are preserved.	2021-11-30 19:03:48 +08:00
rl78.h
rx.h
s12z.h
s390.h	IBM Z: Implement instruction set extensions	2021-02-15 14:32:17 +01:00
score-datadep.h
score-inst.h
sparc.h
spu-insns.h
spu.h
tic4x.h
tic6x-control-registers.h
tic6x-insn-formats.h
tic6x-opcode-table.h	Use bool in include	2021-03-31 10:49:23 +10:30
tic6x.h	Use bool in include	2021-03-31 10:49:23 +10:30
tic30.h
tic54x.h	opcodes: tic54x: namespace exported variables	2021-02-08 18:26:08 -05:00
tilegx.h
tilepro.h
v850.h
vax.h
visium.h
wasm.h
xgate.h