mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
89 lines
3.3 KiB
C
89 lines
3.3 KiB
C
/*> cp1.h <*/
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/* MIPS Simulator FPU (CoProcessor 1) definitions.
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Copyright (C) 1997-2024 Free Software Foundation, Inc.
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Derived from sim-main.h contributed by Cygnus Solutions,
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modified substantially by Ed Satterthwaite of Broadcom Corporation
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(SiByte).
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CP1_H
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#define CP1_H
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/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
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in CPU state (struct sim_cpu), and for FPU functions. */
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#define fcsr_FCC_mask (0xFE800000)
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#define fcsr_FCC_shift (23)
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#define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc)))
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#define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define fcsr_ZERO_mask (0x007C0000)
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#define fcsr_CAUSE_mask (0x0003F000)
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#define fcsr_CAUSE_shift (12)
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#define fcsr_ENABLES_mask (0x00000F80)
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#define fcsr_ENABLES_shift (7)
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#define fcsr_FLAGS_mask (0x0000007C)
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#define fcsr_FLAGS_shift (2)
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#define fcsr_RM_mask (0x00000003)
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#define fcsr_RM_shift (0)
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/* FCSR bits for IEEE754-2008 compliance. */
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#define fcsr_NAN2008_mask (0x00040000)
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#define fcsr_NAN2008_shift (18)
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#define fcsr_ABS2008_mask (0x00080000)
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#define fcsr_ABS2008_shift (19)
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#define fenr_FS (0x00000004)
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/* Macros to update and retrieve the FCSR condition-code bits. This
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is complicated by the fact that there is a hole in the index range
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of the bits within the FCSR register. (Note that the number of bits
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visible depends on the ISA in use, but that is handled elsewhere.) */
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#define SETFCC(cc,v) \
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do { \
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(FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \
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} while (0)
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#define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0)
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/* Read flush-to-zero bit (not right-justified). */
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#define GETFS() ((int)(FCSR & fcsr_FS))
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/* FCSR flag bits definitions and access macros. */
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#define IR 0 /* I: Inexact Result */
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#define UF 1 /* U: UnderFlow */
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#define OF 2 /* O: OverFlow */
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#define DZ 3 /* Z: Division by Zero */
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#define IO 4 /* V: Invalid Operation */
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#define UO 5 /* E: Unimplemented Operation (CAUSE field only) */
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#define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift))
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#define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift))
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#define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift))
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/* Rounding mode bit definitions and access macros. */
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#define FP_RM_NEAREST 0 /* Round to nearest (Round). */
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#define FP_RM_TOZERO 1 /* Round to zero (Trunc). */
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#define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */
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#define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */
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#define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask)
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#endif /* CP1_H */
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