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https://sourceware.org/git/binutils-gdb.git
synced 2024-12-15 04:31:49 +08:00
db7858e227
The cgen code declares some macros/funcs using the trace_xxx prefix, but the code isn't generic and only works with cgen targets. This is blocking the creation of new common trace functions. Let's blindly add cgen_xxx prefixes to all these symbols. Some already use this convention to avoid conflicts, so it makes sense to align them. In the future we might want to move some to the common trace core, but one thing at a time.
320 lines
7.7 KiB
C
320 lines
7.7 KiB
C
# Simulator main loop for m32r. -*- C -*-
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#
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# Copyright (C) 1996-2015 Free Software Foundation, Inc.
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#
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# This file is part of the GNU Simulators.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# Syntax:
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# /bin/sh mainloop.in command
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#
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# Command is one of:
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#
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# init
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# support
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# extract-{simple,scache,pbb}
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# {full,fast}-exec-{simple,scache,pbb}
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#
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# A target need only provide a "full" version of one of simple,scache,pbb.
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# If the target wants it can also provide a fast version of same, or if
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# the slow (full featured) version is `simple', then the fast version can be
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# one of scache/pbb.
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# A target can't provide more than this.
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# However for illustration's sake this file provides examples of all.
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# ??? After a few more ports are done, revisit.
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# Will eventually need to machine generate a lot of this.
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case "x$1" in
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xsupport)
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cat <<EOF
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static INLINE const IDESC *
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extract16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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ARGBUF *abuf, int fast_p)
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{
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const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
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@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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if (! fast_p)
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{
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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@cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
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}
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return id;
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}
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static INLINE const IDESC *
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extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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ARGBUF *abuf, int fast_p)
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{
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const IDESC *id = @cpu@_decode (current_cpu, pc, (USI) insn >> 16, insn, abuf);
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@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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if (! fast_p)
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{
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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@cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
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}
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return id;
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}
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static INLINE SEM_PC
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execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
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{
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SEM_PC vpc;
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if (fast_p)
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{
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#if ! WITH_SEM_SWITCH_FAST
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#if WITH_SCACHE
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vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
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#else
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vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
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#endif
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#else
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abort ();
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#endif /* WITH_SEM_SWITCH_FAST */
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}
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else
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{
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#if ! WITH_SEM_SWITCH_FULL
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ARGBUF *abuf = &sc->argbuf;
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const IDESC *idesc = abuf->idesc;
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const CGEN_INSN *idata = idesc->idata;
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#if WITH_SCACHE_PBB
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int virtual_p = CGEN_INSN_ATTR_VALUE (idata, CGEN_INSN_VIRTUAL);
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#else
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int virtual_p = 0;
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-before */
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if (ARGBUF_PROFILE_P (abuf))
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PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
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/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
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if (PROFILE_MODEL_P (current_cpu)
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&& ARGBUF_PROFILE_P (abuf))
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@cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
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CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
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CGEN_TRACE_INSN (current_cpu, idata,
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(const struct argbuf *) abuf, abuf->addr);
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}
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#if WITH_SCACHE
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
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#else
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vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
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#endif
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if (! virtual_p)
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{
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/* FIXME: call x-after */
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if (PROFILE_MODEL_P (current_cpu)
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&& ARGBUF_PROFILE_P (abuf))
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{
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int cycles;
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cycles = (*idesc->timing->model_fn) (current_cpu, sc);
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@cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
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}
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CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
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}
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#else
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abort ();
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#endif /* WITH_SEM_SWITCH_FULL */
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}
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return vpc;
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}
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EOF
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;;
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xinit)
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# Nothing needed.
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;;
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xextract-simple | xextract-scache)
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cat <<EOF
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{
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if ((pc & 3) != 0)
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{
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/* This only occurs when single stepping.
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The test is unnecessary otherwise, but the cost is teensy,
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compared with decoding/extraction. */
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UHI insn = GETIMEMUHI (current_cpu, pc);
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extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
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}
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else
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{
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USI insn = GETIMEMUSI (current_cpu, pc);
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if ((SI) insn < 0)
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{
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extract32 (current_cpu, pc, insn, sc, FAST_P);
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}
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else
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{
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extract16 (current_cpu, pc, insn >> 16, sc, FAST_P);
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extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P);
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/* The m32r doesn't support parallel execution. */
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if ((insn & 0x8000) != 0
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&& (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
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sim_engine_illegal_insn (current_cpu, pc);
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}
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}
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}
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EOF
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;;
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xextract-pbb)
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# Inputs: current_cpu, pc, sc, max_insns, FAST_P
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# Outputs: sc, pc
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# sc must be left pointing past the last created entry.
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# pc must be left pointing past the last created entry.
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# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
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# to record the vpc of the cti insn.
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# SET_INSN_COUNT(n) must be called to record number of real insns.
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cat <<EOF
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{
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const IDESC *idesc;
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int icount = 0;
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if ((pc & 3) != 0)
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{
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/* This only occurs when single stepping.
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The test is unnecessary otherwise, but the cost is teensy,
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compared with decoding/extraction. */
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UHI insn = GETIMEMUHI (current_cpu, pc);
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idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
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++sc;
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--max_insns;
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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goto Finish;
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}
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}
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while (max_insns > 0)
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{
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USI insn = GETIMEMUSI (current_cpu, pc);
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if ((SI) insn < 0)
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{
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idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
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++sc;
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--max_insns;
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++icount;
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pc += 4;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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}
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else
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{
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idesc = extract16 (current_cpu, pc, insn >> 16, &sc->argbuf, FAST_P);
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++sc;
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--max_insns;
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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/* The m32r doesn't support parallel execution. */
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if ((insn & 0x8000) != 0)
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{
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/* ??? Defer signalling to execution. */
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if ((insn & 0x7fff) != 0x7000) /* parallel nops are ok */
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sim_engine_invalid_insn (current_cpu, pc - 2, 0);
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/* There's no point in processing parallel nops in fast mode.
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We might as well do this test since we've already tested
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that we have a parallel nop. */
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if (0 && FAST_P)
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{
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pc += 2;
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continue;
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}
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}
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else
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{
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/* Non-parallel case.
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While we're guaranteed that there's room to extract the
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insn, when single stepping we can't; the pbb must stop
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after the first insn. */
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if (max_insns == 0)
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break;
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}
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/* We're guaranteed that we can always process 16 bit insns in
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pairs. */
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idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
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++sc;
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--max_insns;
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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}
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}
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Finish:
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SET_INSN_COUNT (icount);
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}
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EOF
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;;
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xfull-exec-* | xfast-exec-*)
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# Inputs: current_cpu, vpc, FAST_P
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# Outputs: vpc
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# vpc is the virtual program counter.
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cat <<EOF
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#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
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#define DEFINE_SWITCH
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#include "sem-switch.c"
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#else
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vpc = execute (current_cpu, vpc, FAST_P);
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#endif
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EOF
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;;
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*)
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echo "Invalid argument to mainloop.in: $1" >&2
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exit 1
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;;
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esac
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