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https://sourceware.org/git/binutils-gdb.git
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b782c65ba1
This commit moves aarch64_linux_memtag_matches_p,
aarch64_linux_set_memtags, aarch64_linux_get_memtag, and
aarch64_linux_memtag_to_string hooks (plus the aarch64_mte_get_atag
function used by them), along with the setting of the memtag granule
size, from aarch64-linux-tdep.c to aarch64-tdep.c, making MTE available
on baremetal targets. Since the aarch64-linux-tdep.c layer inherits
these hooks from aarch64-tdep.c, there is no effective change for
aarch64-linux targets.
Helpers used both by aarch64-tdep.c and by aarch64-linux-tdep.c were
moved from arch/aarch64-mte-linux.{c,h} to new arch/aarch64-mte.{c,h}
files.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Tested-By: Luis Machado <luis.machado@arm.com>
Approved-By: Luis Machado <luis.machado@arm.com>
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
209 lines
6.1 KiB
C++
209 lines
6.1 KiB
C++
/* Common target dependent code for GDB on AArch64 systems.
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Copyright (C) 2009-2024 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AARCH64_TDEP_H
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#define AARCH64_TDEP_H
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#include "arch/aarch64.h"
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#include "displaced-stepping.h"
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#include "infrun.h"
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#include "gdbarch.h"
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/* Forward declarations. */
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struct gdbarch;
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struct regset;
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/* AArch64 Dwarf register numbering. */
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#define AARCH64_DWARF_X0 0
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#define AARCH64_DWARF_SP 31
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#define AARCH64_DWARF_PC 32
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#define AARCH64_DWARF_RA_SIGN_STATE 34
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#define AARCH64_DWARF_V0 64
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#define AARCH64_DWARF_SVE_VG 46
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#define AARCH64_DWARF_SVE_FFR 47
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#define AARCH64_DWARF_SVE_P0 48
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#define AARCH64_DWARF_SVE_Z0 96
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/* Size of integer registers. */
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#define X_REGISTER_SIZE 8
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#define B_REGISTER_SIZE 1
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#define H_REGISTER_SIZE 2
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#define S_REGISTER_SIZE 4
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#define D_REGISTER_SIZE 8
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#define Q_REGISTER_SIZE 16
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/* Total number of general (X) registers. */
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#define AARCH64_X_REGISTER_COUNT 32
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/* Total number of D registers. */
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#define AARCH64_D_REGISTER_COUNT 32
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/* The maximum number of modified instructions generated for one
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single-stepped instruction. */
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#define AARCH64_DISPLACED_MODIFIED_INSNS 1
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/* Target-dependent structure in gdbarch. */
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struct aarch64_gdbarch_tdep : gdbarch_tdep_base
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{
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/* Lowest address at which instructions will appear. */
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CORE_ADDR lowest_pc = 0;
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/* Offset to PC value in jump buffer. If this is negative, longjmp
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support will be disabled. */
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int jb_pc = 0;
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/* And the size of each entry in the buf. */
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size_t jb_elt_size = 0;
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/* Types for AdvSISD registers. */
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struct type *vnq_type = nullptr;
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struct type *vnd_type = nullptr;
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struct type *vns_type = nullptr;
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struct type *vnh_type = nullptr;
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struct type *vnb_type = nullptr;
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struct type *vnv_type = nullptr;
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/* Types for SME ZA tiles and tile slices pseudo-registers. */
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struct type *sme_tile_type_q = nullptr;
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struct type *sme_tile_type_d = nullptr;
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struct type *sme_tile_type_s = nullptr;
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struct type *sme_tile_type_h = nullptr;
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struct type *sme_tile_type_b = nullptr;
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struct type *sme_tile_slice_type_q = nullptr;
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struct type *sme_tile_slice_type_d = nullptr;
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struct type *sme_tile_slice_type_s = nullptr;
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struct type *sme_tile_slice_type_h = nullptr;
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struct type *sme_tile_slice_type_b = nullptr;
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/* Vector of names for SME pseudo-registers. The number of elements is
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different for each distinct svl value. */
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std::vector<std::string> sme_pseudo_names;
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/* syscall record. */
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int (*aarch64_syscall_record) (struct regcache *regcache,
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unsigned long svc_number) = nullptr;
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/* The VQ value for SVE targets, or zero if SVE is not supported. */
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uint64_t vq = 0;
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/* Returns true if the target supports SVE. */
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bool has_sve () const
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{
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return vq != 0;
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}
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int pauth_reg_base = 0;
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/* Number of pauth masks. */
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int pauth_reg_count = 0;
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int ra_sign_state_regnum = 0;
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/* Returns true if the target supports pauth. */
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bool has_pauth () const
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{
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return pauth_reg_base != -1;
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}
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/* First MTE register. This is -1 if no MTE registers are available. */
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int mte_reg_base = 0;
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/* Returns true if the target supports MTE. */
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bool has_mte () const
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{
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return mte_reg_base != -1;
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}
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/* TLS registers. This is -1 if the TLS registers are not available. */
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int tls_regnum_base = 0;
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int tls_register_count = 0;
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bool has_tls() const
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{
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return tls_regnum_base != -1;
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}
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/* The W pseudo-registers. */
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int w_pseudo_base = 0;
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int w_pseudo_count = 0;
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/* SME feature fields. */
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/* Index of the first SME register. This is -1 if SME is not supported. */
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int sme_reg_base = 0;
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/* svg register index. */
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int sme_svg_regnum = 0;
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/* svcr register index. */
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int sme_svcr_regnum = 0;
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/* ZA register index. */
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int sme_za_regnum = 0;
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/* Index of the first SME pseudo-register. This is -1 if SME is not
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supported. */
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int sme_pseudo_base = 0;
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/* Total number of SME pseudo-registers. */
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int sme_pseudo_count = 0;
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/* First tile slice pseudo-register index. */
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int sme_tile_slice_pseudo_base = 0;
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/* Total number of tile slice pseudo-registers. */
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int sme_tile_slice_pseudo_count = 0;
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/* First tile pseudo-register index. */
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int sme_tile_pseudo_base = 0;
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/* The streaming vector quotient (svq) for SME, or zero if SME is not
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supported. */
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size_t sme_svq = 0;
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/* Return true if the target supports SME, and false otherwise. */
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bool has_sme () const
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{
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return sme_svq != 0;
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}
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/* Index of the SME2 ZT0 register. This is -1 if SME2 is not
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supported. */
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int sme2_zt0_regnum = -1;
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/* Return true if the target supports SME2, and false otherwise. */
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bool has_sme2 () const
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{
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return sme2_zt0_regnum > 0;
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}
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};
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const target_desc *aarch64_read_description (const aarch64_features &features);
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aarch64_features
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aarch64_features_from_target_desc (const struct target_desc *tdesc);
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extern int aarch64_process_record (struct gdbarch *gdbarch,
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struct regcache *regcache, CORE_ADDR addr);
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displaced_step_copy_insn_closure_up
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aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs);
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void aarch64_displaced_step_fixup (struct gdbarch *gdbarch,
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displaced_step_copy_insn_closure *dsc,
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CORE_ADDR from, CORE_ADDR to,
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struct regcache *regs, bool completed_p);
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bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch);
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std::optional<CORE_ADDR> aarch64_mte_get_atag (CORE_ADDR address);
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#endif /* aarch64-tdep.h */
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