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A simulator port for the TI PRU I/O processor. v1: https://sourceware.org/ml/gdb-patches/2016-12/msg00143.html v2: https://sourceware.org/ml/gdb-patches/2017-02/msg00397.html v3: https://sourceware.org/ml/gdb-patches/2017-02/msg00516.html v4: https://sourceware.org/ml/gdb-patches/2018-06/msg00484.html v5: https://sourceware.org/ml/gdb-patches/2019-08/msg00584.html v6: https://sourceware.org/ml/gdb-patches/2019-09/msg00036.html gdb/ChangeLog: * NEWS: Mention new simulator port for PRU. sim/ChangeLog: * MAINTAINERS: Add myself as PRU maintainer. * configure: Regenerated. * configure.tgt: Add PRU. sim/common/ChangeLog: * gennltvals.sh: Add PRU libgloss target. * nltvals.def: Regenerate from the latest libgloss sources. sim/pru/ChangeLog: * Makefile.in: New file. * aclocal.m4: Regenerated. * config.in: Regenerated. * configure: Regenerated. * configure.ac: New file. * interp.c: New file. * pru.h: New file. * pru.isa: New file. * sim-main.h: New file.
250 lines
5.5 KiB
Plaintext
250 lines
5.5 KiB
Plaintext
/* Copyright 2016-2019 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of the PRU simulator.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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/*
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PRU Instruction Set Architecture
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INSTRUCTION (NAME,
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SEMANTICS)
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*/
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INSTRUCTION (add,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 + OP2;
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CARRY = (((uint64_t) RS1 + (uint64_t) OP2) >> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (adc,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 + OP2 + CARRY;
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CARRY = (((uint64_t) RS1 + (uint64_t) OP2 + (uint64_t) CARRY)
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>> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (sub,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 - OP2;
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CARRY = (((uint64_t) RS1 - (uint64_t) OP2) >> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (suc,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 - OP2 - CARRY;
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CARRY = (((uint64_t) RS1 - (uint64_t) OP2 - (uint64_t) CARRY)
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>> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (rsb,
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OP2 = (IO ? IMM8 : RS2);
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RD = OP2 - RS1;
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CARRY = (((uint64_t) OP2 - (uint64_t) RS1) >> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (rsc,
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OP2 = (IO ? IMM8 : RS2);
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RD = OP2 - RS1 - CARRY;
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CARRY = (((uint64_t) OP2 - (uint64_t) RS1 - (uint64_t) CARRY)
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>> RD_WIDTH) & 1;
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PC++)
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INSTRUCTION (lsl,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 << (OP2 & 0x1f);
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PC++)
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INSTRUCTION (lsr,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 >> (OP2 & 0x1f);
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PC++)
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INSTRUCTION (and,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 & OP2;
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PC++)
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INSTRUCTION (or,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 | OP2;
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PC++)
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INSTRUCTION (xor,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 ^ OP2;
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PC++)
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INSTRUCTION (not,
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RD = ~RS1;
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PC++)
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INSTRUCTION (min,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 < OP2 ? RS1 : OP2;
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PC++)
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INSTRUCTION (max,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 > OP2 ? RS1 : OP2;
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PC++)
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INSTRUCTION (clr,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 & ~(1u << (OP2 & 0x1f));
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PC++)
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INSTRUCTION (set,
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OP2 = (IO ? IMM8 : RS2);
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RD = RS1 | (1u << (OP2 & 0x1f));
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PC++)
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INSTRUCTION (jmp,
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OP2 = (IO ? IMM16 : RS2);
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PC = OP2)
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INSTRUCTION (jal,
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OP2 = (IO ? IMM16 : RS2);
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RD = PC + 1;
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PC = OP2)
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INSTRUCTION (ldi,
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RD = IMM16;
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PC++)
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INSTRUCTION (halt,
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pru_sim_syscall (sd, cpu);
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PC++)
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INSTRUCTION (slp,
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if (!WAKEONSTATUS)
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{
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RAISE_SIGINT (sd);
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}
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else
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{
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PC++;
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})
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INSTRUCTION (qbgt,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 > RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qbge,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 >= RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qblt,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 < RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qble,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 <= RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qbeq,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 == RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qbne,
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OP2 = (IO ? IMM8 : RS2);
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PC = (OP2 != RS1) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qba,
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OP2 = (IO ? IMM8 : RS2);
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PC = PC + BROFF)
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INSTRUCTION (qbbs,
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OP2 = (IO ? IMM8 : RS2);
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PC = (RS1 & (1u << (OP2 & 0x1f))) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (qbbc,
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OP2 = (IO ? IMM8 : RS2);
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PC = !(RS1 & (1u << (OP2 & 0x1f))) ? (PC + BROFF) : (PC + 1))
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INSTRUCTION (lbbo,
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pru_dmem2reg (cpu, XBBO_BASEREG + (IO ? IMM8 : RS2),
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BURSTLEN, RD_REGN, RDB);
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PC++)
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INSTRUCTION (sbbo,
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pru_reg2dmem (cpu, XBBO_BASEREG + (IO ? IMM8 : RS2),
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BURSTLEN, RD_REGN, RDB);
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PC++)
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INSTRUCTION (lbco,
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pru_dmem2reg (cpu, CTABLE[CB] + (IO ? IMM8 : RS2),
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BURSTLEN, RD_REGN, RDB);
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PC++)
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INSTRUCTION (sbco,
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pru_reg2dmem (cpu, CTABLE[CB] + (IO ? IMM8 : RS2),
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BURSTLEN, RD_REGN, RDB);
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PC++)
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INSTRUCTION (xin,
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DO_XIN (XFR_WBA, RD_REGN, RDB, XFR_LENGTH);
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PC++)
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INSTRUCTION (xout,
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DO_XOUT (XFR_WBA, RD_REGN, RDB, XFR_LENGTH);
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PC++)
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INSTRUCTION (xchg,
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DO_XCHG (XFR_WBA, RD_REGN, RDB, XFR_LENGTH);
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PC++)
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INSTRUCTION (sxin,
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sim_io_eprintf (sd, "SXIN instruction not supported by sim\n");
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RAISE_SIGILL (sd))
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INSTRUCTION (sxout,
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sim_io_eprintf (sd, "SXOUT instruction not supported by sim\n");
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RAISE_SIGILL (sd))
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INSTRUCTION (sxchg,
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sim_io_eprintf (sd, "SXCHG instruction not supported by sim\n");
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RAISE_SIGILL (sd))
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INSTRUCTION (loop,
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OP2 = (IO ? IMM8 + 1 : RS2_w0);
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if (OP2 == 0)
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{
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PC = LOOPEND;
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}
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else
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{
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LOOPTOP = PC + 1;
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LOOPEND = PC + LOOP_JMPOFFS;
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LOOPCNT = OP2;
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LOOP_IN_PROGRESS = 1;
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PC++;
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})
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INSTRUCTION (iloop,
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OP2 = (IO ? IMM8 + 1 : RS2_w0);
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if (OP2 == 0)
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{
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PC = LOOPEND;
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}
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else
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{
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LOOPTOP = PC + 1;
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LOOPEND = PC + LOOP_JMPOFFS;
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LOOPCNT = OP2;
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LOOP_IN_PROGRESS = 1;
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PC++;
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})
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