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c5e3a3641e
For these three relocations, 17 bit signed value should be used, instead of
16 bit. The bitsize field is changed from 16 to 17, this field in aarch64
backend is used for overflow check only.
bfd/
2016-02-26 Renlin Li <renlin.li@arm.com>
* elfnn-aarch64.c (elfNN_aarch64_howto_table): Fix signed overflow
check for MOVW_SABS_G0, MOVW_SABS_G1, MOVW_SABS_G2.
ld/
2016-02-26 Renlin Li <renlin.li@arm.com>
* testsuite/ld-aarch64/aarch64-elf.exp: Run new testcases.
* testsuite/ld-aarch64/emit-relocs-270.d: Update to use new boundary.
* testsuite/ld-aarch64/emit-relocs-271.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-272.d: Likewise.
* testsuite/ld-aarch64/emit-relocs-270-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-270-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-271-overflow.s: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.d: New.
* testsuite/ld-aarch64/emit-relocs-272-overflow.s: New.
14 lines
550 B
Makefile
14 lines
550 B
Makefile
#source: emit-relocs-271.s
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#ld: -T relocs.ld --defsym tempy=0xffffffff --defsym tempy2=0x674500 --defsym tempy3=-0x100000000 -e0 --emit-relocs
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#objdump: -dr
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#...
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+10000: 8a000000 and x0, x0, x0
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+10004: 92400000 and x0, x0, #0x1
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+10008: d2bfffe4 mov x4, #0xffff0000 // #4294901760
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10008: R_AARCH64_MOVW_SABS_G1 tempy
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+1000c: d2a00ce7 mov x7, #0x670000 // #6750208
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1000c: R_AARCH64_MOVW_SABS_G1 tempy2
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+10010: 92bffff1 mov x17, #0xffffffff0000ffff // #-4294901761
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10010: R_AARCH64_MOVW_SABS_G1 tempy3
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