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fa85fb9a1b
The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to ensure that destination register in a relaxed ldr instruction is always X0. The mask has an off by one error resulting in the most significant bit of the destination register being retained in the relaxed instruction. The issue generally appears when the compiler emits TLS accesses code under high register pressure resulting in a broken code sequence.
14 lines
215 B
ArmAsm
14 lines
215 B
ArmAsm
.global var
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.section .tdata
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var:
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.word 2
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.text
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adrp x0, :tlsdesc:var
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ldr x17, [x0, #:tlsdesc_lo12:var]
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add x0, x0, :tlsdesc_lo12:var
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.tlsdesccall var
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blr x1
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mrs x1, tpidr_el0
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add x0, x1, x0
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ldr w0, [x0]
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