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d137b254d9
All funcs already call other funcs that don't return. The mips port is the only exception because its generic exception handler can return in the case of normal exceptions. So while the exceptions its signal handler triggers doesn't return, we can't express that conditional logic. So add some useless abort calls to make the compiler happy.
233 lines
7.0 KiB
C
233 lines
7.0 KiB
C
#ifndef MN10300_SIM_H
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#define MN10300_SIM_H
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/* For compatibility, until all functions converted to passing
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SIM_DESC as an argument */
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extern SIM_DESC simulator;
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typedef struct
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{
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uint32_t low, high;
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} dword;
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typedef uint32_t reg_t;
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struct simops
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{
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long opcode;
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long mask;
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void (*func)();
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int length;
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int format;
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int numops;
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int operands[16];
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};
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/* The current state of the processor; registers, memory, etc. */
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struct _state
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{
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reg_t regs[32]; /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
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lir, lar, mdrq, plus some room for processor
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specific regs. */
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union
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{
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reg_t fs[32]; /* FS0-31 */
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dword fd[16]; /* FD0,2,...,30 */
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} fpregs;
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/* All internal state modified by signal_exception() that may need to be
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rolled back for passing moment-of-exception image back to gdb. */
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reg_t exc_trigger_regs[32];
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reg_t exc_suspend_regs[32];
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int exc_suspended;
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#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
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#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
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#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
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};
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extern struct _state State;
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#define PC (State.regs[REG_PC])
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#define SP (State.regs[REG_SP])
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#define PSW (State.regs[11])
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#define PSW_Z 0x1
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#define PSW_N 0x2
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#define PSW_C 0x4
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#define PSW_V 0x8
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#define PSW_IE LSBIT (11)
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#define PSW_LM LSMASK (10, 8)
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#define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
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#define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
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#define REG_D0 0
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#define REG_A0 4
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#define REG_SP 8
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#define REG_PC 9
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#define REG_MDR 10
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#define REG_PSW 11
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#define REG_LIR 12
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#define REG_LAR 13
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#define REG_MDRQ 14
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#define REG_E0 15
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#define REG_SSP 23
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#define REG_MSP 24
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#define REG_USP 25
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#define REG_MCRH 26
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#define REG_MCRL 27
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#define REG_MCVF 28
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#define REG_FPCR 29
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#define FPCR (State.regs[REG_FPCR])
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#define FCC_MASK LSMASK (21, 18)
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#define RM_MASK LSMASK (17, 16) /* Must always be zero. */
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#define EC_MASK LSMASK (14, 10)
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#define EE_MASK LSMASK ( 9, 5)
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#define EF_MASK LSMASK ( 4, 0)
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#define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
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#define FCC_L LSBIT (21)
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#define FCC_G LSBIT (20)
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#define FCC_E LSBIT (19)
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#define FCC_U LSBIT (18)
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#define EC_V LSBIT (14)
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#define EC_Z LSBIT (13)
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#define EC_O LSBIT (12)
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#define EC_U LSBIT (11)
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#define EC_I LSBIT (10)
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#define EE_V LSBIT (9)
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#define EE_Z LSBIT (8)
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#define EE_O LSBIT (7)
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#define EE_U LSBIT (6)
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#define EE_I LSBIT (5)
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#define EF_V LSBIT (4)
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#define EF_Z LSBIT (3)
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#define EF_O LSBIT (2)
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#define EF_U LSBIT (1)
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#define EF_I LSBIT (0)
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#define PSW_FE LSBIT(20)
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#define FPU_DISABLED !(PSW & PSW_FE)
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#define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
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#define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
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#define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
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#define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
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#define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
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#define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
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#define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
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#define FETCH32(a,b,c,d) \
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((a)+((b)<<8)+((c)<<16)+((d)<<24))
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#define FETCH24(a,b,c) \
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((a)+((b)<<8)+((c)<<16))
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#define FETCH16(a,b) ((a)+((b)<<8))
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#define load_byte(ADDR) \
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sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define load_half(ADDR) \
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sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define load_word(ADDR) \
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sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
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#define load_dword(ADDR) \
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u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
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PC, read_map, (ADDR)))
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static INLINE2 dword
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u642dw (uint64_t dw)
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{
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dword r;
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r.low = (uint32_t)dw;
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r.high = (uint32_t)(dw >> 32);
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return r;
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}
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#define store_byte(ADDR, DATA) \
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sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#define store_half(ADDR, DATA) \
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sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#define store_word(ADDR, DATA) \
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sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), (DATA))
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#define store_dword(ADDR, DATA) \
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sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
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PC, write_map, (ADDR), dw2u64 (DATA))
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static INLINE2 uint64_t
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dw2u64 (dword data)
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{
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return data.low | (((uint64_t)data.high) << 32);
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}
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/* Bring data in from the cold */
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#define IMEM8(EA) \
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(sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA)))
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#define IMEM8_IMMED(EA, N) \
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(sim_core_read_aligned_1(STATE_CPU (SD, 0), EA, exec_map, (EA) + (N)))
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/* Function declarations. */
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INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
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INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
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INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
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INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
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INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
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INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
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INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
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void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig)
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ATTRIBUTE_NORETURN;
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void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
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void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
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void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
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void fpu_disabled_exception (SIM_DESC, sim_cpu *, address_word);
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void fpu_unimp_exception (SIM_DESC, sim_cpu *, address_word);
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void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
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extern const struct fp_prec_t
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{
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void (* reg2val) (const void *, sim_fpu *);
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int (* round) (sim_fpu *);
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void (* val2reg) (const sim_fpu *, void *);
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} fp_single_prec, fp_double_prec;
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#define FP_SINGLE (&fp_single_prec)
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#define FP_DOUBLE (&fp_double_prec)
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void fpu_rsqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
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void fpu_sqrt (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
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void fpu_cmp (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
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void fpu_add (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_sub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_mul (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_div (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_fmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_fmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
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void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
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#endif
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