mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-09 04:21:49 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
854 lines
22 KiB
C
854 lines
22 KiB
C
/* The common simulator framework for GDB, the GNU Debugger.
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Copyright 2002-2024 Free Software Foundation, Inc.
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Contributed by Andrew Cagney and Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef SIM_CORE_C
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#define SIM_CORE_C
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/* This must come before any other includes. */
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#include "defs.h"
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#include <stdlib.h>
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#include "libiberty.h"
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#include "sim-main.h"
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#include "sim-assert.h"
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#include "sim-signal.h"
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#if (WITH_HW)
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#include "sim-hw.h"
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#endif
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/* "core" module install handler.
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This is called via sim_module_install to install the "core"
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subsystem into the simulator. */
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#if EXTERN_SIM_CORE_P
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static MODULE_INIT_FN sim_core_init;
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static MODULE_UNINSTALL_FN sim_core_uninstall;
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#endif
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#if EXTERN_SIM_CORE_P
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SIM_RC
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sim_core_install (SIM_DESC sd)
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{
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* establish the other handlers */
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sim_module_add_uninstall_fn (sd, sim_core_uninstall);
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sim_module_add_init_fn (sd, sim_core_init);
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/* establish any initial data structures - none */
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return SIM_RC_OK;
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}
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#endif
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/* Uninstall the "core" subsystem from the simulator. */
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#if EXTERN_SIM_CORE_P
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static void
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sim_core_uninstall (SIM_DESC sd)
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{
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sim_core *core = STATE_CORE (sd);
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unsigned map;
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/* blow away any mappings */
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for (map = 0; map < nr_maps; map++) {
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sim_core_mapping *curr = core->common.map[map].first;
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while (curr != NULL) {
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sim_core_mapping *tbd = curr;
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curr = curr->next;
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if (tbd->free_buffer != NULL) {
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SIM_ASSERT (tbd->buffer != NULL);
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free (tbd->free_buffer);
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}
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free (tbd);
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}
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core->common.map[map].first = NULL;
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}
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}
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#endif
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#if EXTERN_SIM_CORE_P
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static SIM_RC
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sim_core_init (SIM_DESC sd)
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{
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/* Nothing to do */
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return SIM_RC_OK;
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}
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#endif
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#ifndef SIM_CORE_SIGNAL
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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sim_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
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#endif
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#if EXTERN_SIM_CORE_P
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void
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sim_core_signal (SIM_DESC sd,
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sim_cpu *cpu,
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sim_cia cia,
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unsigned map,
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int nr_bytes,
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address_word addr,
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transfer_type transfer,
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sim_core_signals sig)
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{
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const char *copy = (transfer == read_transfer ? "read" : "write");
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address_word ip = CIA_ADDR (cia);
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switch (sig)
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{
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case sim_core_unmapped_signal:
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sim_io_eprintf (sd, "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
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nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
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sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGSEGV);
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break;
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case sim_core_unaligned_signal:
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sim_io_eprintf (sd, "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
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nr_bytes, copy, (unsigned long) addr, (unsigned long) ip);
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sim_engine_halt (sd, cpu, NULL, cia, sim_stopped, SIM_SIGBUS);
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break;
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default:
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sim_engine_abort (sd, cpu, cia,
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"sim_core_signal - internal error - bad switch");
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}
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}
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#endif
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#if EXTERN_SIM_CORE_P
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static sim_core_mapping *
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new_sim_core_mapping (SIM_DESC sd,
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int level,
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int space,
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address_word addr,
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address_word nr_bytes,
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unsigned modulo,
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struct hw *device,
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void *buffer,
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void *free_buffer)
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{
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sim_core_mapping *new_mapping = ZALLOC (sim_core_mapping);
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/* common */
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new_mapping->level = level;
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new_mapping->space = space;
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new_mapping->base = addr;
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new_mapping->nr_bytes = nr_bytes;
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new_mapping->bound = addr + (nr_bytes - 1);
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new_mapping->mask = modulo - 1;
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new_mapping->buffer = buffer;
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new_mapping->free_buffer = free_buffer;
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new_mapping->device = device;
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return new_mapping;
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}
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#endif
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#if EXTERN_SIM_CORE_P
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static void
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sim_core_map_attach (SIM_DESC sd,
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sim_core_map *access_map,
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int level,
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int space,
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address_word addr,
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address_word nr_bytes,
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unsigned modulo,
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struct hw *client, /*callback/default*/
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void *buffer, /*raw_memory*/
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void *free_buffer) /*raw_memory*/
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{
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/* find the insertion point for this additional mapping and then
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insert */
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sim_core_mapping *next_mapping;
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sim_core_mapping **last_mapping;
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SIM_ASSERT ((client == NULL) != (buffer == NULL));
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SIM_ASSERT ((client == NULL) >= (free_buffer != NULL));
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/* actually do occasionally get a zero size map */
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if (nr_bytes == 0)
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{
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#if (WITH_HW)
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sim_hw_abort (sd, client, "called on sim_core_map_attach with size zero");
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#endif
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sim_io_error (sd, "called on sim_core_map_attach with size zero");
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}
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/* find the insertion point (between last/next) */
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next_mapping = access_map->first;
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last_mapping = &access_map->first;
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while (next_mapping != NULL
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&& (next_mapping->level < level
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|| (next_mapping->level == level
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&& next_mapping->bound < addr)))
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{
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/* provided levels are the same */
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/* assert: next_mapping->base > all bases before next_mapping */
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/* assert: next_mapping->bound >= all bounds before next_mapping */
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last_mapping = &next_mapping->next;
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next_mapping = next_mapping->next;
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}
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/* check insertion point correct */
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SIM_ASSERT (next_mapping == NULL || next_mapping->level >= level);
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if (next_mapping != NULL && next_mapping->level == level
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&& next_mapping->base < (addr + (nr_bytes - 1)))
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{
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#if WITH_HW
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sim_hw_abort (sd, client, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
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space,
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(long) addr,
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(long) (addr + (nr_bytes - 1)),
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(long) nr_bytes,
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next_mapping->space,
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(long) next_mapping->base,
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(long) next_mapping->bound,
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(long) next_mapping->nr_bytes);
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#endif
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sim_io_error (sd, "memory map %d:0x%lx..0x%lx (%ld bytes) overlaps %d:0x%lx..0x%lx (%ld bytes)",
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space,
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(long) addr,
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(long) (addr + (nr_bytes - 1)),
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(long) nr_bytes,
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next_mapping->space,
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(long) next_mapping->base,
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(long) next_mapping->bound,
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(long) next_mapping->nr_bytes);
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}
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/* create/insert the new mapping */
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*last_mapping = new_sim_core_mapping (sd,
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level,
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space, addr, nr_bytes, modulo,
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client, buffer, free_buffer);
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(*last_mapping)->next = next_mapping;
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}
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#endif
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/* Attach memory or a memory mapped device to the simulator.
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See sim-core.h for a full description. */
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#if EXTERN_SIM_CORE_P
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void
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sim_core_attach (SIM_DESC sd,
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sim_cpu *cpu,
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int level,
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unsigned mapmask,
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int space,
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address_word addr,
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address_word nr_bytes,
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unsigned modulo,
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struct hw *client,
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void *optional_buffer)
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{
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sim_core *memory = STATE_CORE (sd);
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unsigned map;
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void *buffer;
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void *free_buffer;
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/* check for for attempt to use unimplemented per-processor core map */
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if (cpu != NULL)
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sim_io_error (sd, "sim_core_map_attach - processor specific memory map not yet supported");
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if (client != NULL && modulo != 0)
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{
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#if (WITH_HW)
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sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo and callback memory conflict");
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#endif
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sim_io_error (sd, "sim_core_attach - internal error - modulo and callback memory conflict");
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}
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if (modulo != 0)
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{
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unsigned mask = modulo - 1;
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/* any zero bits */
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while (mask >= sizeof (uint64_t)) /* minimum modulo */
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{
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if ((mask & 1) == 0)
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mask = 0;
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else
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mask >>= 1;
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}
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if (mask != sizeof (uint64_t) - 1)
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{
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#if (WITH_HW)
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sim_hw_abort (sd, client, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
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#endif
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sim_io_error (sd, "sim_core_attach - internal error - modulo %lx not power of two", (long) modulo);
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}
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}
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/* verify consistency between device and buffer */
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if (client != NULL && optional_buffer != NULL)
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{
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#if (WITH_HW)
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sim_hw_abort (sd, client, "sim_core_attach - internal error - conflicting buffer and attach arguments");
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#endif
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sim_io_error (sd, "sim_core_attach - internal error - conflicting buffer and attach arguments");
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}
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if (client == NULL)
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{
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if (optional_buffer == NULL)
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{
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int padding = (addr % sizeof (uint64_t));
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unsigned long bytes = (modulo == 0 ? nr_bytes : modulo) + padding;
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free_buffer = zalloc (bytes);
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buffer = (char*) free_buffer + padding;
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}
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else
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{
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buffer = optional_buffer;
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free_buffer = NULL;
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}
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}
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else
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{
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/* a device */
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buffer = NULL;
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free_buffer = NULL;
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}
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/* attach the region to all applicable access maps */
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for (map = 0;
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map < nr_maps;
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map++)
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{
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if (mapmask & (1 << map))
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{
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sim_core_map_attach (sd, &memory->common.map[map],
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level, space, addr, nr_bytes, modulo,
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client, buffer, free_buffer);
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free_buffer = NULL;
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}
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}
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/* Just copy this map to each of the processor specific data structures.
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FIXME - later this will be replaced by true processor specific
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maps. */
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{
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int i;
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for (i = 0; i < MAX_NR_PROCESSORS; i++)
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{
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CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
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}
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}
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}
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#endif
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/* Remove any memory reference related to this address */
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#if EXTERN_SIM_CORE_P
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static void
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sim_core_map_detach (SIM_DESC sd,
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sim_core_map *access_map,
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int level,
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int space,
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address_word addr)
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{
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sim_core_mapping **entry;
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for (entry = &access_map->first;
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(*entry) != NULL;
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entry = &(*entry)->next)
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{
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if ((*entry)->base == addr
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&& (*entry)->level == level
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&& (*entry)->space == space)
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{
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sim_core_mapping *dead = (*entry);
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(*entry) = dead->next;
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if (dead->free_buffer != NULL)
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free (dead->free_buffer);
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free (dead);
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return;
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}
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}
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}
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#endif
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#if EXTERN_SIM_CORE_P
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void
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sim_core_detach (SIM_DESC sd,
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sim_cpu *cpu,
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int level,
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int address_space,
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address_word addr)
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{
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sim_core *memory = STATE_CORE (sd);
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unsigned map;
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for (map = 0; map < nr_maps; map++)
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{
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sim_core_map_detach (sd, &memory->common.map[map],
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level, address_space, addr);
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}
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/* Just copy this update to each of the processor specific data
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structures. FIXME - later this will be replaced by true
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processor specific maps. */
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{
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int i;
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for (i = 0; i < MAX_NR_PROCESSORS; i++)
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{
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CPU_CORE (STATE_CPU (sd, i))->common = STATE_CORE (sd)->common;
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}
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}
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}
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#endif
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STATIC_INLINE_SIM_CORE\
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(sim_core_mapping *)
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sim_core_find_mapping (sim_core_common *core,
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unsigned map,
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address_word addr,
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unsigned nr_bytes,
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transfer_type transfer,
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int abort, /*either 0 or 1 - hint to inline/-O */
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sim_cpu *cpu, /* abort => cpu != NULL */
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sim_cia cia)
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{
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sim_core_mapping *mapping = core->map[map].first;
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ASSERT ((addr & (nr_bytes - 1)) == 0); /* must be aligned */
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ASSERT ((addr + (nr_bytes - 1)) >= addr); /* must not wrap */
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ASSERT (!abort || cpu != NULL); /* abort needs a non null CPU */
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while (mapping != NULL)
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{
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if (addr >= mapping->base
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&& (addr + (nr_bytes - 1)) <= mapping->bound)
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return mapping;
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mapping = mapping->next;
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}
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if (abort)
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{
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SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map, nr_bytes, addr, transfer,
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sim_core_unmapped_signal);
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}
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return NULL;
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}
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STATIC_INLINE_SIM_CORE\
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(void *)
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sim_core_translate (sim_core_mapping *mapping,
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address_word addr)
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{
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return (void *)((uint8_t *) mapping->buffer
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+ ((addr - mapping->base) & mapping->mask));
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}
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#if EXTERN_SIM_CORE_P
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/* See include/sim/sim.h. */
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char *
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sim_memory_map (SIM_DESC sd)
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{
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sim_core *core = STATE_CORE (sd);
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unsigned map;
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char *s1, *s2, *entry;
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s1 = xstrdup (
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"<?xml version='1.0'?>\n"
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"<!DOCTYPE memory-map PUBLIC '+//IDN gnu.org//DTD GDB Memory Map V1.0//EN'"
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" 'http://sourceware.org/gdb/gdb-memory-map.dtd'>\n"
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"<memory-map>\n");
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for (map = 0; map < nr_maps; ++map)
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{
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sim_core_mapping *mapping;
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for (mapping = core->common.map[map].first;
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mapping != NULL;
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mapping = mapping->next)
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{
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/* GDB can only handle a single address space. */
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if (mapping->level != 0)
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continue;
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entry = xasprintf ("<memory type='ram' start='%#" PRIxTW "' "
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"length='%#" PRIxTW "'/>\n",
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mapping->base, mapping->nr_bytes);
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/* The sim memory map is organized by access, not by addresses.
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So a RWX memory map will have three independent mappings.
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GDB's format cannot support overlapping regions, so we have
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to filter those out.
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Further, GDB can only handle RX ("rom") or RWX ("ram") mappings.
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We just emit "ram" everywhere to keep it simple. If GDB ever
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gains support for more stuff, we can expand this.
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Using strstr is kind of hacky, but as long as the map is not huge
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(we're talking <10K), should be fine. */
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if (strstr (s1, entry) == NULL)
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{
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s2 = concat (s1, entry, NULL);
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free (s1);
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s1 = s2;
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}
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free (entry);
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}
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}
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s2 = concat (s1, "</memory-map>", NULL);
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free (s1);
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return s2;
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}
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#endif
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#if EXTERN_SIM_CORE_P
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unsigned
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sim_core_read_buffer (SIM_DESC sd,
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sim_cpu *cpu,
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unsigned map,
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void *buffer,
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address_word addr,
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unsigned len)
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{
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sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
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unsigned count = 0;
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while (count < len)
|
|
{
|
|
address_word raddr = addr + count;
|
|
sim_core_mapping *mapping =
|
|
sim_core_find_mapping (core, map,
|
|
raddr, /*nr-bytes*/1,
|
|
read_transfer,
|
|
0 /*dont-abort*/, NULL, NULL_CIA);
|
|
if (mapping == NULL)
|
|
break;
|
|
#if (WITH_HW)
|
|
if (mapping->device != NULL)
|
|
{
|
|
int nr_bytes = len - count;
|
|
if (raddr + nr_bytes - 1> mapping->bound)
|
|
nr_bytes = mapping->bound - raddr + 1;
|
|
/* If the access was initiated by a cpu, pass it down so errors can
|
|
be propagated properly. For other sources (e.g. GDB or DMA), we
|
|
can only signal errors via the return value. */
|
|
if (cpu)
|
|
{
|
|
sim_cia cia = cpu ? CPU_PC_GET (cpu) : NULL_CIA;
|
|
sim_cpu_hw_io_read_buffer (cpu, cia, mapping->device,
|
|
(unsigned_1*)buffer + count,
|
|
mapping->space,
|
|
raddr,
|
|
nr_bytes);
|
|
}
|
|
else if (sim_hw_io_read_buffer (sd, mapping->device,
|
|
(unsigned_1*)buffer + count,
|
|
mapping->space,
|
|
raddr,
|
|
nr_bytes) != nr_bytes)
|
|
break;
|
|
count += nr_bytes;
|
|
continue;
|
|
}
|
|
#endif
|
|
((unsigned_1*)buffer)[count] =
|
|
*(unsigned_1*)sim_core_translate (mapping, raddr);
|
|
count += 1;
|
|
}
|
|
return count;
|
|
}
|
|
#endif
|
|
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
unsigned
|
|
sim_core_write_buffer (SIM_DESC sd,
|
|
sim_cpu *cpu,
|
|
unsigned map,
|
|
const void *buffer,
|
|
address_word addr,
|
|
unsigned len)
|
|
{
|
|
sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
|
|
unsigned count = 0;
|
|
while (count < len)
|
|
{
|
|
address_word raddr = addr + count;
|
|
sim_core_mapping *mapping =
|
|
sim_core_find_mapping (core, map,
|
|
raddr, /*nr-bytes*/1,
|
|
write_transfer,
|
|
0 /*dont-abort*/, NULL, NULL_CIA);
|
|
if (mapping == NULL)
|
|
break;
|
|
#if (WITH_HW)
|
|
if (mapping->device != NULL)
|
|
{
|
|
int nr_bytes = len - count;
|
|
if (raddr + nr_bytes - 1 > mapping->bound)
|
|
nr_bytes = mapping->bound - raddr + 1;
|
|
/* If the access was initiated by a cpu, pass it down so errors can
|
|
be propagated properly. For other sources (e.g. GDB or DMA), we
|
|
can only signal errors via the return value. */
|
|
if (cpu)
|
|
{
|
|
sim_cia cia = cpu ? CPU_PC_GET (cpu) : NULL_CIA;
|
|
sim_cpu_hw_io_write_buffer (cpu, cia, mapping->device,
|
|
(unsigned_1*)buffer + count,
|
|
mapping->space,
|
|
raddr,
|
|
nr_bytes);
|
|
}
|
|
else if (sim_hw_io_write_buffer (sd, mapping->device,
|
|
(unsigned_1*)buffer + count,
|
|
mapping->space,
|
|
raddr,
|
|
nr_bytes) != nr_bytes)
|
|
break;
|
|
count += nr_bytes;
|
|
continue;
|
|
}
|
|
#endif
|
|
*(unsigned_1*)sim_core_translate (mapping, raddr) =
|
|
((unsigned_1*)buffer)[count];
|
|
count += 1;
|
|
}
|
|
return count;
|
|
}
|
|
#endif
|
|
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
void
|
|
sim_core_set_xor (SIM_DESC sd,
|
|
sim_cpu *cpu,
|
|
int is_xor)
|
|
{
|
|
/* set up the XOR map if required. */
|
|
if (WITH_XOR_ENDIAN) {
|
|
{
|
|
sim_core *core = STATE_CORE (sd);
|
|
sim_cpu_core *cpu_core = (cpu != NULL ? CPU_CORE (cpu) : NULL);
|
|
if (cpu_core != NULL)
|
|
{
|
|
int i = 1;
|
|
unsigned mask;
|
|
if (is_xor)
|
|
mask = WITH_XOR_ENDIAN - 1;
|
|
else
|
|
mask = 0;
|
|
while (i - 1 < WITH_XOR_ENDIAN)
|
|
{
|
|
cpu_core->byte_xor[i-1] = mask;
|
|
mask = (mask << 1) & (WITH_XOR_ENDIAN - 1);
|
|
i = (i << 1);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (is_xor)
|
|
core->byte_xor = WITH_XOR_ENDIAN - 1;
|
|
else
|
|
core->byte_xor = 0;
|
|
}
|
|
}
|
|
}
|
|
else {
|
|
if (is_xor)
|
|
sim_engine_abort (sd, NULL, NULL_CIA,
|
|
"Attempted to enable xor-endian mode when permanently disabled.");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
static void
|
|
reverse_n (unsigned_1 *dest,
|
|
const unsigned_1 *src,
|
|
int nr_bytes)
|
|
{
|
|
int i;
|
|
for (i = 0; i < nr_bytes; i++)
|
|
{
|
|
dest [nr_bytes - i - 1] = src [i];
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
unsigned
|
|
sim_core_xor_read_buffer (SIM_DESC sd,
|
|
sim_cpu *cpu,
|
|
unsigned map,
|
|
void *buffer,
|
|
address_word addr,
|
|
unsigned nr_bytes)
|
|
{
|
|
address_word byte_xor
|
|
= (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->byte_xor[0]);
|
|
if (!WITH_XOR_ENDIAN || !byte_xor)
|
|
return sim_core_read_buffer (sd, cpu, map, buffer, addr, nr_bytes);
|
|
else
|
|
/* only break up transfers when xor-endian is both selected and enabled */
|
|
{
|
|
unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero-sized array */
|
|
unsigned nr_transfered = 0;
|
|
address_word start = addr;
|
|
unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
|
|
address_word stop;
|
|
/* initial and intermediate transfers are broken when they cross
|
|
an XOR endian boundary */
|
|
while (nr_transfered + nr_this_transfer < nr_bytes)
|
|
/* initial/intermediate transfers */
|
|
{
|
|
/* since xor-endian is enabled stop^xor defines the start
|
|
address of the transfer */
|
|
stop = start + nr_this_transfer - 1;
|
|
SIM_ASSERT (start <= stop);
|
|
SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
|
|
if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
|
|
!= nr_this_transfer)
|
|
return nr_transfered;
|
|
reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
|
|
nr_transfered += nr_this_transfer;
|
|
nr_this_transfer = WITH_XOR_ENDIAN;
|
|
start = stop + 1;
|
|
}
|
|
/* final transfer */
|
|
nr_this_transfer = nr_bytes - nr_transfered;
|
|
stop = start + nr_this_transfer - 1;
|
|
SIM_ASSERT (stop == (addr + nr_bytes - 1));
|
|
if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
|
|
!= nr_this_transfer)
|
|
return nr_transfered;
|
|
reverse_n (&((unsigned_1*)buffer)[nr_transfered], x, nr_this_transfer);
|
|
return nr_bytes;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
unsigned
|
|
sim_core_xor_write_buffer (SIM_DESC sd,
|
|
sim_cpu *cpu,
|
|
unsigned map,
|
|
const void *buffer,
|
|
address_word addr,
|
|
unsigned nr_bytes)
|
|
{
|
|
address_word byte_xor
|
|
= (cpu == NULL ? STATE_CORE (sd)->byte_xor : CPU_CORE (cpu)->byte_xor[0]);
|
|
if (!WITH_XOR_ENDIAN || !byte_xor)
|
|
return sim_core_write_buffer (sd, cpu, map, buffer, addr, nr_bytes);
|
|
else
|
|
/* only break up transfers when xor-endian is both selected and enabled */
|
|
{
|
|
unsigned_1 x[WITH_XOR_ENDIAN + 1]; /* +1 to avoid zero sized array */
|
|
unsigned nr_transfered = 0;
|
|
address_word start = addr;
|
|
unsigned nr_this_transfer = (WITH_XOR_ENDIAN - (addr & ~(WITH_XOR_ENDIAN - 1)));
|
|
address_word stop;
|
|
/* initial and intermediate transfers are broken when they cross
|
|
an XOR endian boundary */
|
|
while (nr_transfered + nr_this_transfer < nr_bytes)
|
|
/* initial/intermediate transfers */
|
|
{
|
|
/* since xor-endian is enabled stop^xor defines the start
|
|
address of the transfer */
|
|
stop = start + nr_this_transfer - 1;
|
|
SIM_ASSERT (start <= stop);
|
|
SIM_ASSERT ((stop ^ byte_xor) <= (start ^ byte_xor));
|
|
reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
|
|
if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
|
|
!= nr_this_transfer)
|
|
return nr_transfered;
|
|
nr_transfered += nr_this_transfer;
|
|
nr_this_transfer = WITH_XOR_ENDIAN;
|
|
start = stop + 1;
|
|
}
|
|
/* final transfer */
|
|
nr_this_transfer = nr_bytes - nr_transfered;
|
|
stop = start + nr_this_transfer - 1;
|
|
SIM_ASSERT (stop == (addr + nr_bytes - 1));
|
|
reverse_n (x, &((unsigned_1*)buffer)[nr_transfered], nr_this_transfer);
|
|
if (sim_core_read_buffer (sd, cpu, map, x, stop ^ byte_xor, nr_this_transfer)
|
|
!= nr_this_transfer)
|
|
return nr_transfered;
|
|
return nr_bytes;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#if EXTERN_SIM_CORE_P
|
|
void *
|
|
sim_core_trans_addr (SIM_DESC sd,
|
|
sim_cpu *cpu,
|
|
unsigned map,
|
|
address_word addr)
|
|
{
|
|
sim_core_common *core = (cpu == NULL ? &STATE_CORE (sd)->common : &CPU_CORE (cpu)->common);
|
|
sim_core_mapping *mapping =
|
|
sim_core_find_mapping (core, map,
|
|
addr, /*nr-bytes*/1,
|
|
write_transfer,
|
|
0 /*dont-abort*/, NULL, NULL_CIA);
|
|
if (mapping == NULL)
|
|
return NULL;
|
|
return sim_core_translate (mapping, addr);
|
|
}
|
|
#endif
|
|
|
|
|
|
|
|
/* define the read/write 1/2/4/8/16/word functions */
|
|
|
|
#define N 16
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 8
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 7
|
|
#define M 8
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 6
|
|
#define M 8
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 5
|
|
#define M 8
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 4
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 3
|
|
#define M 4
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 2
|
|
#include "sim-n-core.h"
|
|
|
|
#define N 1
|
|
#include "sim-n-core.h"
|
|
|
|
#endif
|