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This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
87 lines
3.0 KiB
C++
87 lines
3.0 KiB
C++
/* Target-dependent header for the RISC-V architecture, for GDB, the
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GNU Debugger.
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Copyright (C) 2018 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_TDEP_H
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#define RISCV_TDEP_H
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#include "arch/riscv.h"
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/* RiscV register numbers. */
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enum
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{
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RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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RISCV_RA_REGNUM = 1, /* Return Address. */
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RISCV_SP_REGNUM = 2, /* Stack Pointer. */
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RISCV_GP_REGNUM = 3, /* Global Pointer. */
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RISCV_TP_REGNUM = 4, /* Thread Pointer. */
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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RISCV_NUM_INTEGER_REGS = 32,
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
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RISCV_FA0_REGNUM = 43,
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RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
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RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
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RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
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#define DECLARE_CSR(name, num) \
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RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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RISCV_LAST_CSR_REGNUM = 4160,
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RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
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RISCV_PRIV_REGNUM = 4161,
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RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
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};
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/* RISC-V specific per-architecture information. */
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struct gdbarch_tdep
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{
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/* Features about the target that impact how the gdbarch is configured.
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Two gdbarch instances are compatible only if this field matches. */
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struct riscv_gdbarch_features features;
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/* ISA-specific data types. */
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struct type *riscv_fpreg_d_type = nullptr;
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};
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/* Return the width in bytes of the general purpose registers for GDBARCH.
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Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
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RV128. */
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extern int riscv_isa_xlen (struct gdbarch *gdbarch);
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/* Return the width in bytes of the floating point registers for GDBARCH.
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If this architecture has no floating point registers, then return 0.
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Possible values are 4, 8, or 16 for depending on which of single, double
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or quad floating point support is available. */
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extern int riscv_isa_flen (struct gdbarch *gdbarch);
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/* Single step based on where the current instruction will take us. */
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extern std::vector<CORE_ADDR> riscv_software_single_step
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(struct regcache *regcache);
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#endif /* RISCV_TDEP_H */
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