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Egeyar Bagcioglu 57b64c4103 [aarch64] - Only use MOV for disassembly when shifter op is LSL #0
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'.  However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.

2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>

opcodes:
	PR 23193
        PR 19721
        * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
	encoding as MOV if the shift operation is a left shift of zero.

gas:
	PR 23193
	PR 19721
	* testsuite/gas/aarch64/pr19721.s: Add new test cases.
	* testsuite/gas/aarch64/pr19721.d: Correct existing test
	cases and add new ones.
2018-12-03 17:34:33 +00:00
bfd Automatic date update in version.in 2018-12-03 00:00:31 +00:00
binutils Update the assembler to use a version of 3 when generating the header of the .debug_line section. 2018-12-03 17:26:41 +00:00
config Fix a typo in iconv.m4. 2018-11-09 16:08:10 +00:00
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gas [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 2018-12-03 17:34:33 +00:00
gdb [gdb/testsuite] Add gdb-caching-proc.exp testcase 2018-12-01 08:56:56 +01:00
gold gold: Get alignment of uncompressed section from ch_addralign 2018-12-02 05:43:04 -08:00
gprof
include RISC-V: Add .insn CA support. 2018-11-27 11:29:23 -08:00
intl Fix a typo in iconv.m4. 2018-11-09 16:08:10 +00:00
ld x86: Delay setting the iplt section alignment 2018-12-01 06:35:03 -08:00
libdecnumber
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opcodes [aarch64] - Only use MOV for disassembly when shifter op is LSL #0 2018-12-03 17:34:33 +00:00
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		   README for GNU development tools

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