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0e39210161
Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR relocation attached as an alias to `jr $25' and convert the jump to an equivalent branch where possible, consequently covering the MIPSr6 architecture for the purpose of this optimization too. bfd/ * elfxx-mips.c (mips_elf_perform_relocation): Also handle the `jalr $0, $25' instruction encoding. gas/ * testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions. * testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6 encoding patterns. * testsuite/gas/mips/jalr4-n64.d: Likewise. * testsuite/gas/mips/mipsr6@jalr4.d: New test. * testsuite/gas/mips/mipsr6@jalr4-n32.d: New test. * testsuite/gas/mips/mipsr6@jalr4-n64.d: New test. ld/ * testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25' instructions. * testsuite/ld-mips-elf/jalr4-r6.dd: New test. * testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
26 lines
726 B
Plaintext
26 lines
726 B
Plaintext
.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> 04110017 bal 0+000060 <bar0>
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 10000015 b 0+000060 <bar0>
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 10000013 b 0+000060 <bar0>
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 0320f809 jalr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 03200009 jr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 03200009 jr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 0320f809 jalr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 03200009 jr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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[0-9a-f]+ <[^>]*> 03200009 jr t9
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[0-9a-f]+ <[^>]*> 00000000 nop
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\.\.\.
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\.\.\.
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\.\.\.
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\.\.\.
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