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812 lines
22 KiB
C
812 lines
22 KiB
C
/* Simulation code for the CR16 processor.
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Copyright (C) 2008-2017 Free Software Foundation, Inc.
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Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <inttypes.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include "bfd.h"
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#include "gdb/callback.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "gdb/sim-cr16.h"
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#include "gdb/signals.h"
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#include "opcode/cr16.h"
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int cr16_debug;
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uint32 OP[4];
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uint32 sign_flag;
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static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size);
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static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops);
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#define MAX_HASH 16
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struct hash_entry
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{
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struct hash_entry *next;
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uint32 opcode;
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uint32 mask;
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int format;
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int size;
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struct simops *ops;
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};
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struct hash_entry hash_table[MAX_HASH+1];
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INLINE static long
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hash(unsigned long long insn, int format)
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{
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unsigned int i = 4, tmp;
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if (format)
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{
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while ((insn >> i) != 0) i +=4;
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return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key. */
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}
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return ((insn & 0xF)); /* Use last 4 bits as hask key. */
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}
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INLINE static struct hash_entry *
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lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size)
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{
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uint32 mask;
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struct hash_entry *h;
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h = &hash_table[hash(ins,1)];
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mask = (((1 << (32 - h->mask)) -1) << h->mask);
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/* Adjuest mask for branch with 2 word instructions. */
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if ((h->ops->mnimonic != NULL) &&
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((streq(h->ops->mnimonic,"b") && h->size == 2)))
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mask = 0xff0f0000;
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while ((ins & mask) != (BIN(h->opcode, h->mask)))
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{
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if (h->next == NULL)
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sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGILL);
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h = h->next;
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mask = (((1 << (32 - h->mask)) -1) << h->mask);
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/* Adjuest mask for branch with 2 word instructions. */
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if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
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mask = 0xff0f0000;
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}
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return (h);
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}
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INLINE static void
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get_operands (operand_desc *s, uint64 ins, int isize, int nops)
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{
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uint32 i, opn = 0, start_bit = 0, op_type = 0;
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int32 op_size = 0, mask = 0;
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if (isize == 1) /* Trunkcate the extra 16 bits of INS. */
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ins = ins >> 16;
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for (i=0; i < 4; ++i,++opn)
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{
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if (s[opn].op_type == dummy) break;
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op_type = s[opn].op_type;
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start_bit = s[opn].shift;
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op_size = cr16_optab[op_type].bit_size;
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switch (op_type)
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{
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case imm3: case imm4: case imm5: case imm6:
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{
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if (isize == 1)
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OP[i] = ((ins >> 4) & ((1 << op_size) -1));
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else
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OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
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if (OP[i] & ((long)1 << (op_size -1)))
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{
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sign_flag = 1;
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OP[i] = ~(OP[i]) + 1;
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}
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OP[i] = (unsigned long int)(OP[i] & (((long)1 << op_size) -1));
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}
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break;
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case uimm3: case uimm3_1: case uimm4_1:
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switch (isize)
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{
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case 1:
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OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
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case 2:
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OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
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default: /* for case 3. */
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OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
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break;
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}
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break;
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case uimm4:
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switch (isize)
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{
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case 1:
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if (start_bit == 20)
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OP[i] = ((ins >> 4) & ((1 << op_size) -1));
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else
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OP[i] = (ins & ((1 << op_size) -1));
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break;
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case 2:
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OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
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break;
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case 3:
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OP[i] = ((ins >> (start_bit + 16)) & ((1 << op_size) -1));
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break;
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default:
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OP[i] = ((ins >> start_bit) & ((1 << op_size) -1));
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break;
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}
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break;
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case imm16: case uimm16:
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OP[i] = ins & 0xFFFF;
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break;
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case uimm20: case imm20:
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OP[i] = ins & (((long)1 << op_size) - 1);
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break;
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case imm32: case uimm32:
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OP[i] = ins & 0xFFFFFFFF;
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break;
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case uimm5: break; /*NOT USED. */
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OP[i] = ins & ((1 << op_size) - 1); break;
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case disps5:
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OP[i] = (ins >> 4) & ((1 << 4) - 1);
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OP[i] = (OP[i] * 2) + 2;
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if (OP[i] & ((long)1 << 5))
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{
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sign_flag = 1;
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OP[i] = ~(OP[i]) + 1;
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OP[i] = (unsigned long int)(OP[i] & 0x1F);
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}
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break;
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case dispe9:
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OP[i] = ((((ins >> 8) & 0xf) << 4) | (ins & 0xf));
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OP[i] <<= 1;
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if (OP[i] & ((long)1 << 8))
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{
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sign_flag = 1;
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OP[i] = ~(OP[i]) + 1;
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OP[i] = (unsigned long int)(OP[i] & 0xFF);
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}
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break;
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case disps17:
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OP[i] = (ins & 0xFFFF);
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if (OP[i] & 1)
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{
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OP[i] = (OP[i] & 0xFFFE);
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sign_flag = 1;
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OP[i] = ~(OP[i]) + 1;
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OP[i] = (unsigned long int)(OP[i] & 0xFFFF);
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}
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break;
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case disps25:
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if (isize == 2)
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OP[i] = (ins & 0xFFFFFF);
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else
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OP[i] = (ins & 0xFFFF) | (((ins >> 24) & 0xf) << 16) |
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(((ins >> 16) & 0xf) << 20);
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if (OP[i] & 1)
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{
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OP[i] = (OP[i] & 0xFFFFFE);
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sign_flag = 1;
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OP[i] = ~(OP[i]) + 1;
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OP[i] = (unsigned long int)(OP[i] & 0xFFFFFF);
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}
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break;
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case abs20:
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if (isize == 3)
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OP[i] = (ins) & 0xFFFFF;
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else
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OP[i] = (ins >> start_bit) & 0xFFFFF;
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break;
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case abs24:
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if (isize == 3)
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OP[i] = ((ins & 0xFFFF) | (((ins >> 16) & 0xf) << 20)
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| (((ins >> 24) & 0xf) << 16));
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else
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OP[i] = (ins >> 16) & 0xFFFFFF;
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break;
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case rra:
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case rbase: break; /* NOT USED. */
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case rbase_disps20: case rbase_dispe20:
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case rpbase_disps20: case rpindex_disps20:
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OP[i] = ((((ins >> 24)&0xf) << 16)|((ins) & 0xFFFF));
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OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
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break;
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case rpbase_disps0:
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OP[i] = 0; /* 4 bit disp const. */
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OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
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break;
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case rpbase_dispe4:
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OP[i] = ((ins >> 8) & 0xF) * 2; /* 4 bit disp const. */
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OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
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break;
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case rpbase_disps4:
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OP[i] = ((ins >> 8) & 0xF); /* 4 bit disp const. */
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OP[++i] = (ins) & 0xF; /* get 4 bit for reg. */
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break;
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case rpbase_disps16:
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OP[i] = (ins) & 0xFFFF;
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OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
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break;
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case rpindex_disps0:
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OP[i] = 0;
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OP[++i] = (ins >> 4) & 0xF; /* get 4 bit for reg. */
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OP[++i] = (ins >> 8) & 0x1; /* get 1 bit for index-reg. */
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break;
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case rpindex_disps14:
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OP[i] = (ins) & 0x3FFF;
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OP[++i] = (ins >> 14) & 0x1; /* get 1 bit for index-reg. */
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OP[++i] = (ins >> 16) & 0xF; /* get 4 bit for reg. */
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case rindex7_abs20:
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case rindex8_abs20:
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OP[i] = (ins) & 0xFFFFF;
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OP[++i] = (ins >> 24) & 0x1; /* get 1 bit for index-reg. */
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OP[++i] = (ins >> 20) & 0xF; /* get 4 bit for reg. */
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break;
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case regr: case regp: case pregr: case pregrp:
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switch(isize)
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{
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case 1:
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if (start_bit == 20) OP[i] = (ins >> 4) & 0xF;
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else if (start_bit == 16) OP[i] = ins & 0xF;
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break;
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case 2: OP[i] = (ins >> start_bit) & 0xF; break;
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case 3: OP[i] = (ins >> (start_bit + 16)) & 0xF; break;
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}
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break;
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case cc:
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{
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if (isize == 1) OP[i] = (ins >> 4) & 0xF;
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else if (isize == 2) OP[i] = (ins >> start_bit) & 0xF;
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else OP[i] = (ins >> (start_bit + 16)) & 0xF;
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break;
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}
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default: break;
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}
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/* For ESC on uimm4_1 operand. */
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if (op_type == uimm4_1)
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if (OP[i] == 9)
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OP[i] = -1;
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/* For increment by 1. */
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if ((op_type == pregr) || (op_type == pregrp))
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OP[i] += 1;
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}
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/* FIXME: for tracing, update values that need to be updated each
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instruction decode cycle */
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State.trace.psw = PSR;
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}
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static int
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do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode)
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{
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struct hash_entry *h;
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#ifdef DEBUG
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if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
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sim_io_printf (sd, "do_long 0x%x\n", mcode);
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#endif
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h = lookup_hash (sd, cpu, mcode, 1);
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if ((h == NULL) || (h->opcode == 0))
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return 0;
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if (h->size == 3)
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mcode = (mcode << 16) | RW (PC + 4);
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/* Re-set OP list. */
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OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
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/* for push/pop/pushrtn with RA instructions. */
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if ((h->format & REG_LIST) && (mcode & 0x800000))
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OP[2] = 1; /* Set 1 for RA operand. */
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/* numops == 0 means, no operands. */
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if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
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get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
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//State.ins_type = h->flags;
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(h->ops->func) (sd, cpu);
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return h->size;
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}
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static sim_cia
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cr16_pc_get (sim_cpu *cpu)
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{
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return PC;
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}
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static void
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cr16_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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SIM_DESC sd = CPU_STATE (cpu);
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SET_PC (pc);
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}
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int);
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static int cr16_reg_store (SIM_CPU *, int, unsigned char *, int);
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb,
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struct bfd *abfd, char * const *argv)
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{
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struct simops *s;
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struct hash_entry *h;
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static int init_p = 0;
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char **p;
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int i;
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SIM_DESC sd = sim_state_alloc (kind, cb);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* The parser will print an error message for us, so we silently return. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Check for/establish the a reference program image. */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Configure/verify the target byte order and other runtime
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configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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CPU_REG_FETCH (cpu) = cr16_reg_fetch;
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CPU_REG_STORE (cpu) = cr16_reg_store;
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CPU_PC_FETCH (cpu) = cr16_pc_get;
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CPU_PC_STORE (cpu) = cr16_pc_set;
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}
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/* The CR16 has an interrupt controller at 0xFC00, but we don't currently
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handle that. Revisit if anyone ever implements operating mode. */
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/* cr16 memory: There are three separate cr16 memory regions IMEM,
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UMEM and DMEM. The IMEM and DMEM are further broken down into
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blocks (very like VM pages). This might not match the hardware,
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but it matches what the toolchain currently expects. Ugh. */
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sim_do_commandf (sd, "memory-size %#x", 20 * 1024 * 1024);
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/* put all the opcodes in the hash table. */
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if (!init_p++)
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{
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for (s = Simops; s->func; s++)
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{
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switch(32 - s->mask)
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{
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case 0x4:
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0x7:
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if (((s->opcode << 1) >> 4) != 0)
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h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
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else
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h = &hash_table[hash((s->opcode << 1), 0)];
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break;
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case 0x8:
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if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0x9:
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if (((s->opcode >> 1) >> 4) != 0)
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h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
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else
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h = &hash_table[hash((s->opcode >> 1), 0)];
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break;
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case 0xa:
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if ((s->opcode >> 8) != 0)
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h = &hash_table[hash(s->opcode >> 8, 0)];
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else if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
|
|
h = &hash_table[hash(s->opcode, 0)];
|
|
break;
|
|
|
|
case 0xc:
|
|
if ((s->opcode >> 8) != 0)
|
|
h = &hash_table[hash(s->opcode >> 8, 0)];
|
|
else if ((s->opcode >> 4) != 0)
|
|
h = &hash_table[hash(s->opcode >> 4, 0)];
|
|
else
|
|
h = &hash_table[hash(s->opcode, 0)];
|
|
break;
|
|
|
|
case 0xd:
|
|
if (((s->opcode >> 1) >> 8) != 0)
|
|
h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
|
|
else if (((s->opcode >> 1) >> 4) != 0)
|
|
h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
|
|
else
|
|
h = &hash_table[hash((s->opcode >>1), 0)];
|
|
break;
|
|
|
|
case 0x10:
|
|
if ((s->opcode >> 0xc) != 0)
|
|
h = &hash_table[hash(s->opcode >> 12, 0)];
|
|
else if ((s->opcode >> 8) != 0)
|
|
h = &hash_table[hash(s->opcode >> 8, 0)];
|
|
else if ((s->opcode >> 4) != 0)
|
|
h = &hash_table[hash(s->opcode >> 4, 0)];
|
|
else
|
|
h = &hash_table[hash(s->opcode, 0)];
|
|
break;
|
|
|
|
case 0x14:
|
|
if ((s->opcode >> 16) != 0)
|
|
h = &hash_table[hash(s->opcode >> 16, 0)];
|
|
else if ((s->opcode >> 12) != 0)
|
|
h = &hash_table[hash(s->opcode >> 12, 0)];
|
|
else if ((s->opcode >> 8) != 0)
|
|
h = &hash_table[hash(s->opcode >> 8, 0)];
|
|
else if ((s->opcode >> 4) != 0)
|
|
h = &hash_table[hash(s->opcode >> 4, 0)];
|
|
else
|
|
h = &hash_table[hash(s->opcode, 0)];
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* go to the last entry in the chain. */
|
|
while (h->next)
|
|
h = h->next;
|
|
|
|
if (h->ops)
|
|
{
|
|
h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
|
|
if (!h->next)
|
|
perror ("malloc failure");
|
|
|
|
h = h->next;
|
|
}
|
|
h->ops = s;
|
|
h->mask = s->mask;
|
|
h->opcode = s->opcode;
|
|
h->format = s->format;
|
|
h->size = s->size;
|
|
}
|
|
}
|
|
|
|
return sd;
|
|
}
|
|
|
|
static void
|
|
step_once (SIM_DESC sd, SIM_CPU *cpu)
|
|
{
|
|
uint32 curr_ins_size = 0;
|
|
uint64 mcode = RLW (PC);
|
|
|
|
State.pc_changed = 0;
|
|
|
|
curr_ins_size = do_run (sd, cpu, mcode);
|
|
|
|
#if CR16_DEBUG
|
|
sim_io_printf (sd, "INS: PC=0x%X, mcode=0x%X\n", PC, mcode);
|
|
#endif
|
|
|
|
if (curr_ins_size == 0)
|
|
sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2));
|
|
else if (!State.pc_changed)
|
|
SET_PC (PC + (curr_ins_size * 2)); /* For word instructions. */
|
|
|
|
#if 0
|
|
/* Check for a breakpoint trap on this instruction. This
|
|
overrides any pending branches or loops */
|
|
if (PSR_DB && PC == DBS)
|
|
{
|
|
SET_BPC (PC);
|
|
SET_BPSR (PSR);
|
|
SET_PC (SDBT_VECTOR_START);
|
|
}
|
|
#endif
|
|
|
|
/* Writeback all the DATA / PC changes */
|
|
SLOT_FLUSH ();
|
|
}
|
|
|
|
void
|
|
sim_engine_run (SIM_DESC sd,
|
|
int next_cpu_nr, /* ignore */
|
|
int nr_cpus, /* ignore */
|
|
int siggnal)
|
|
{
|
|
sim_cpu *cpu;
|
|
|
|
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
|
|
|
|
cpu = STATE_CPU (sd, 0);
|
|
|
|
switch (siggnal)
|
|
{
|
|
case 0:
|
|
break;
|
|
case GDB_SIGNAL_BUS:
|
|
case GDB_SIGNAL_SEGV:
|
|
SET_PC (PC);
|
|
SET_PSR (PSR);
|
|
JMP (AE_VECTOR_START);
|
|
SLOT_FLUSH ();
|
|
break;
|
|
case GDB_SIGNAL_ILL:
|
|
SET_PC (PC);
|
|
SET_PSR (PSR);
|
|
SET_HW_PSR ((PSR & (PSR_C_BIT)));
|
|
JMP (RIE_VECTOR_START);
|
|
SLOT_FLUSH ();
|
|
break;
|
|
default:
|
|
/* just ignore it */
|
|
break;
|
|
}
|
|
|
|
while (1)
|
|
{
|
|
step_once (sd, cpu);
|
|
if (sim_events_tick (sd))
|
|
sim_events_process (sd);
|
|
}
|
|
}
|
|
|
|
SIM_RC
|
|
sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
|
|
char * const *argv, char * const *env)
|
|
{
|
|
bfd_vma start_address;
|
|
|
|
/* reset all state information */
|
|
memset (&State, 0, sizeof (State));
|
|
|
|
/* There was a hack here to copy the values of argc and argv into r0
|
|
and r1. The values were also saved into some high memory that
|
|
won't be overwritten by the stack (0x7C00). The reason for doing
|
|
this was to allow the 'run' program to accept arguments. Without
|
|
the hack, this is not possible anymore. If the simulator is run
|
|
from the debugger, arguments cannot be passed in, so this makes
|
|
no difference. */
|
|
|
|
/* set PC */
|
|
if (abfd != NULL)
|
|
start_address = bfd_get_start_address (abfd);
|
|
else
|
|
start_address = 0x0;
|
|
#ifdef DEBUG
|
|
if (cr16_debug)
|
|
sim_io_printf (sd, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
|
|
#endif
|
|
{
|
|
SIM_CPU *cpu = STATE_CPU (sd, 0);
|
|
SET_CREG (PC_CR, start_address);
|
|
}
|
|
|
|
SLOT_FLUSH ();
|
|
return SIM_RC_OK;
|
|
}
|
|
|
|
static uint32
|
|
cr16_extract_unsigned_integer (unsigned char *addr, int len)
|
|
{
|
|
uint32 retval;
|
|
unsigned char * p;
|
|
unsigned char * startaddr = (unsigned char *)addr;
|
|
unsigned char * endaddr = startaddr + len;
|
|
|
|
retval = 0;
|
|
|
|
for (p = endaddr; p > startaddr;)
|
|
retval = (retval << 8) | *--p;
|
|
|
|
return retval;
|
|
}
|
|
|
|
static void
|
|
cr16_store_unsigned_integer (unsigned char *addr, int len, uint32 val)
|
|
{
|
|
unsigned char *p;
|
|
unsigned char *startaddr = addr;
|
|
unsigned char *endaddr = startaddr + len;
|
|
|
|
for (p = startaddr; p < endaddr;)
|
|
{
|
|
*p++ = val & 0xff;
|
|
val >>= 8;
|
|
}
|
|
}
|
|
|
|
static int
|
|
cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
|
{
|
|
int size;
|
|
switch ((enum sim_cr16_regs) rn)
|
|
{
|
|
case SIM_CR16_R0_REGNUM:
|
|
case SIM_CR16_R1_REGNUM:
|
|
case SIM_CR16_R2_REGNUM:
|
|
case SIM_CR16_R3_REGNUM:
|
|
case SIM_CR16_R4_REGNUM:
|
|
case SIM_CR16_R5_REGNUM:
|
|
case SIM_CR16_R6_REGNUM:
|
|
case SIM_CR16_R7_REGNUM:
|
|
case SIM_CR16_R8_REGNUM:
|
|
case SIM_CR16_R9_REGNUM:
|
|
case SIM_CR16_R10_REGNUM:
|
|
case SIM_CR16_R11_REGNUM:
|
|
cr16_store_unsigned_integer (memory, 2, GPR (rn - SIM_CR16_R0_REGNUM));
|
|
size = 2;
|
|
break;
|
|
case SIM_CR16_R12_REGNUM:
|
|
case SIM_CR16_R13_REGNUM:
|
|
case SIM_CR16_R14_REGNUM:
|
|
case SIM_CR16_R15_REGNUM:
|
|
cr16_store_unsigned_integer (memory, 4, GPR (rn - SIM_CR16_R0_REGNUM));
|
|
size = 4;
|
|
break;
|
|
case SIM_CR16_PC_REGNUM:
|
|
case SIM_CR16_ISP_REGNUM:
|
|
case SIM_CR16_USP_REGNUM:
|
|
case SIM_CR16_INTBASE_REGNUM:
|
|
case SIM_CR16_PSR_REGNUM:
|
|
case SIM_CR16_CFG_REGNUM:
|
|
case SIM_CR16_DBS_REGNUM:
|
|
case SIM_CR16_DCR_REGNUM:
|
|
case SIM_CR16_DSR_REGNUM:
|
|
case SIM_CR16_CAR0_REGNUM:
|
|
case SIM_CR16_CAR1_REGNUM:
|
|
cr16_store_unsigned_integer (memory, 4, CREG (rn - SIM_CR16_PC_REGNUM));
|
|
size = 4;
|
|
break;
|
|
default:
|
|
size = 0;
|
|
break;
|
|
}
|
|
return size;
|
|
}
|
|
|
|
static int
|
|
cr16_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
|
|
{
|
|
SIM_DESC sd = CPU_STATE (cpu);
|
|
int size;
|
|
switch ((enum sim_cr16_regs) rn)
|
|
{
|
|
case SIM_CR16_R0_REGNUM:
|
|
case SIM_CR16_R1_REGNUM:
|
|
case SIM_CR16_R2_REGNUM:
|
|
case SIM_CR16_R3_REGNUM:
|
|
case SIM_CR16_R4_REGNUM:
|
|
case SIM_CR16_R5_REGNUM:
|
|
case SIM_CR16_R6_REGNUM:
|
|
case SIM_CR16_R7_REGNUM:
|
|
case SIM_CR16_R8_REGNUM:
|
|
case SIM_CR16_R9_REGNUM:
|
|
case SIM_CR16_R10_REGNUM:
|
|
case SIM_CR16_R11_REGNUM:
|
|
SET_GPR (rn - SIM_CR16_R0_REGNUM, cr16_extract_unsigned_integer (memory, 2));
|
|
size = 2;
|
|
break;
|
|
case SIM_CR16_R12_REGNUM:
|
|
case SIM_CR16_R13_REGNUM:
|
|
case SIM_CR16_R14_REGNUM:
|
|
case SIM_CR16_R15_REGNUM:
|
|
SET_GPR32 (rn - SIM_CR16_R0_REGNUM, cr16_extract_unsigned_integer (memory, 2));
|
|
size = 4;
|
|
break;
|
|
case SIM_CR16_PC_REGNUM:
|
|
case SIM_CR16_ISP_REGNUM:
|
|
case SIM_CR16_USP_REGNUM:
|
|
case SIM_CR16_INTBASE_REGNUM:
|
|
case SIM_CR16_PSR_REGNUM:
|
|
case SIM_CR16_CFG_REGNUM:
|
|
case SIM_CR16_DBS_REGNUM:
|
|
case SIM_CR16_DCR_REGNUM:
|
|
case SIM_CR16_DSR_REGNUM:
|
|
case SIM_CR16_CAR0_REGNUM:
|
|
case SIM_CR16_CAR1_REGNUM:
|
|
SET_CREG (rn - SIM_CR16_PC_REGNUM, cr16_extract_unsigned_integer (memory, 4));
|
|
size = 4;
|
|
break;
|
|
default:
|
|
size = 0;
|
|
break;
|
|
}
|
|
SLOT_FLUSH ();
|
|
return size;
|
|
}
|