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561a72d4dd
binutils-gdb/include/ChangeLog
Tamar Christina 561a72d4dd Modify AArch64 Assembly and disassembly functions to be able to fail and report why. 
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:17:36 +01:00

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2018-05-15 Tamar Christina <tamar.christina@arm.com>
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
2018-05-15 Francois H. Theron <francois.theron@netronome.com>
* opcode/nfp.h: Use uint64_t instead of bfd_vma.
2018-05-10 John Darrington <john@darrington.wattle.id.au>
* elf/common.h (EM_S12Z): New macro.
2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
2018-05-08 Jim Wilson <jimw@sifive.com>
* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
(MATCH_C_SRAI64, MASK_C_SRAI64): New.
(MATCH_C_SLLI64, MASK_C_SLLI64): New.
2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
(vle_num_opcodes): Likewise.
(spe2_num_opcodes): Likewise.
2018-05-04 Alan Modra <amodra@gmail.com>
* ansidecl.h: Import from gcc.
* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
to s_name.
(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
2018-04-30 Francois H. Theron <francois.theron@netronome.com>
* dis-asm.h: Added print_nfp_disassembler_options prototype.
* elf/common.h: Added EM_NFP, officially assigned. See Google Group
Generic System V Application Binary Interface.
* elf/nfp.h: New, for NFP support.
* opcode/nfp.h: New, for NFP support.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
R_ARM_TLS_IE32_FDPIC.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
(R_ARM_FUNCDESC)
(R_ARM_FUNCDESC_VALUE): Define new relocations.
2018-04-25 Christophe Lyon <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>
* elf/arm.h (EF_ARM_FDPIC): New.
2018-04-18 Alan Modra <amodra@gmail.com>
* coff/mipspe.h: Delete.
2018-04-18 Alan Modra <amodra@gmail.com>
* aout/dynix3.h: Delete.
2018-04-17 Andrew Sadek <andrew.sadek.se@gmail.com>
Microblaze Target: PIC data text relative
* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
* elf/microblaze.h (Add 3 new relocations):
R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
and R_MICROBLAZE_TEXTREL_32_LO for relax function.
2018-04-17 Alan Modra <amodra@gmail.com>
* elf/i370.h: Revert removal.
* elf/i860.h: Likewise.
* elf/i960.h: Likewise.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/sparc.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* aout/host.h: Remove m68k-aout and m68k-coff support.
* aout/hp300hpux.h: Delete.
* coff/apollo.h: Delete.
* coff/aux-coff.h: Delete.
* coff/m68k.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* dis-asm.h: Remove sh5 and sh64 support.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/internal.h: Remove w65 support.
* coff/w65.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/we32k.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/internal.h: Remove m88k support.
* coff/m88k.h: Delete.
* opcode/m88k.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* elf/i370.h: Delete.
* opcode/i370.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/h8500.h: Delete.
* coff/internal.h: Remove h8500 support.
2018-04-16 Alan Modra <amodra@gmail.com>
* coff/h8300.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* ieee.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* aout/host.h: Remove newsos3 support.
2018-04-16 Alan Modra <amodra@gmail.com>
* nlm/ChangeLog-9315: Delete.
* nlm/alpha-ext.h: Delete.
* nlm/common.h: Delete.
* nlm/external.h: Delete.
* nlm/i386-ext.h: Delete.
* nlm/internal.h: Delete.
* nlm/ppc-ext.h: Delete.
* nlm/sparc32-ext.h: Delete.
2018-04-16 Alan Modra <amodra@gmail.com>
* opcode/tahoe.h: Delete.
2018-04-11 Alan Modra <amodra@gmail.com>
* aout/adobe.h: Delete.
* aout/reloc.h: Delete.
* coff/i860.h: Delete.
* coff/i960.h: Delete.
* elf/i860.h: Delete.
* elf/i960.h: Delete.
* opcode/i860.h: Delete.
* opcode/i960.h: Delete.
* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
* aout/ar.h (ARMAGB): Remove.
* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
union internal_auxent): Remove i960 support.
2018-04-09 Alan Modra <amodra@gmail.com>
* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
2018-03-28 Renlin Li <renlin.li@arm.com>
PR ld/22970
* elf/aarch64.h: Add relocation number for
R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
2018-03-28 Nick Clifton <nickc@redhat.com>
PR 22988
* opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_SVE_ADDR_R.
2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
* elf/common.h (DF_1_KMOD): New.
(DF_1_WEAKFILTER): Likewise.
(DF_1_NOCOMMON): Likewise.
2018-03-14 Kito Cheng <kito.cheng@gmail.com>
* opcode/riscv.h (OP_MASK_FUNCT3): New.
(OP_SH_FUNCT3): Likewise.
(OP_MASK_FUNCT7): Likewise.
(OP_SH_FUNCT7): Likewise.
(OP_MASK_OP2): Likewise.
(OP_SH_OP2): Likewise.
(OP_MASK_CFUNCT4): Likewise.
(OP_SH_CFUNCT4): Likewise.
(OP_MASK_CFUNCT3): Likewise.
(OP_SH_CFUNCT3): Likewise.
(riscv_insn_types): Likewise.
2018-03-13 Nick Clifton <nickc@redhat.com>
PR 22113
* coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
field.
2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
* opcode/i386 (OLDGCC_COMPAT): Removed.
2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
2018-02-20 Maciej W. Rozycki <macro@mips.com>
* opcode/mips.h: Remove `M' operand code.
2018-02-12 Zebediah Figura <z.figura12@gmail.com>
* coff/msdos.h: New header.
* coff/pe.h: Move common defines to msdos.h.
* coff/powerpc.h: Likewise.
2018-01-13 Nick Clifton <nickc@redhat.com>
2.30 branch created.
2018-01-11 H.J. Lu <hongjiu.lu@intel.com>
PR ld/22393
* bfdlink.h (bfd_link_info): Add separate_code.
2018-01-04 Jim Wilson <jimw@sifive.com>
* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL. Rename
DECLARE_CSR entry. Add alias to map sbadaddr to CSR_STVAL.
(CSR_MBADADDR): Rename to CSR_MTVAL. Rename DECLARE_CSR entry.
Add alias to map mbadaddr to CSR_MTVAL.
2018-01-03 Alan Modra <amodra@gmail.com>
Update year range in copyright notice of all files.
For older changes see ChangeLog-2017
Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
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