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https://sourceware.org/git/binutils-gdb.git
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df136d64fa
This patch generates EH info for the new _notoc linkage stubs, to support unwinding from asynchronous signal handlers. Unwinding through the __tls_get_addr_opt stub was already supported, but that was just a single stub. With multiple stubs the EH opcodes need to be emitted and sized when iterating over stubs, so this is done when emitting and sizing the stub code. Emitting the CIEs and FDEs is done when sizing the stubs, as we did before in order to have the linker generated FDEs indexed in .eh_frame_hdr. I moved the final tweaks to FDEs from ppc64_elf_finish_dynamic_sections to ppc64_elf_build_stubs simply because it's tidier to be done with them at that point. bfd/ * elf64-ppc.c (struct map_stub): Delete tls_get_addr_opt_bctrl. Add lr_restore, eh_size and eh_base. (eh_advance, eh_advance_size): New functions. (build_tls_get_addr_stub): Emit EH info for stub. (ppc_build_one_stub): Likewise for _notoc stubs. (ppc_size_one_stub): Size EH info for stub. (group_sections): Init new map_stub fields. (stub_eh_frame_size): Delete. (ppc64_elf_size_stubs): Size EH info for stubs. Set up dummy EH program for stubs. (ppc64_elf_build_stubs): Reinit new map_stub fields. Set FDE offset to stub section here.. (ppc64_elf_finish_dynamic_sections): ..rather than here. ld/ * testsuite/ld-powerpc/notoc.s: Generate some cfi. * testsuite/ld-powerpc/notoc.d: Adjust. * testsuite/ld-powerpc/notoc.wf: New file. * testsuite/ld-powerpc/powerpc.exp: Run "ext" and "notoc" tests as run_ld_link_tests rather than run_dump_test.
103 lines
3.6 KiB
Makefile
103 lines
3.6 KiB
Makefile
#source: notoc.s
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#as: -a64
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#ld: --no-plt-localentry -T ext.lnk
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#objdump: -d
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#target: powerpc64*-*-*
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.*
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Disassembly of section \.text:
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.* <.*\.long_branch\.f1>:
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (7c 00 00 48|48 00 00 7c) b .* <f1>
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.* <.*\.long_branch\.g1>:
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (8c 00 00 48|48 00 00 8c) b .* <g1>
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.* <.*\.plt_branch\.ext>:
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (ff 7f 80 3d|3d 80 7f ff) lis r12,32767
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.*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535
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.*: (c6 07 9c 79|79 9c 07 c6) rldicr r28,r12,32,31
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.*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439
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.*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320
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.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (20 04 80 4e|4e 80 04 20) bctr
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.* <.*\.long_branch\.f2>:
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (64 00 8b 39|39 8b 00 64) addi r12,r11,100
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.*: (58 00 00 48|48 00 00 58) b .* <f2>
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.* <.*\.long_branch\.g2>:
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (80 00 8b 39|39 8b 00 80) addi r12,r11,128
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.*: (74 00 00 48|48 00 00 74) b .* <g2>
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\.\.\.
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.* <f1>:
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.*: (01 00 00 48|48 00 00 01) bl .* <f1>
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.*: (bd ff ff 4b|4b ff ff bd) bl .* <.*\.long_branch\.f2>
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.*: (11 00 00 48|48 00 00 11) bl .* <g1>
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.*: (cd ff ff 4b|4b ff ff cd) bl .* <.*\.long_branch\.g2>
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.*: (81 ff ff 4b|4b ff ff 81) bl .* <.*\.plt_branch\.ext>
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <g1>:
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.*: (a9 ff ff 4b|4b ff ff a9) bl .* <.*\.long_branch\.f2>
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.*: (e5 ff ff 4b|4b ff ff e5) bl .* <f1>
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.*: (b9 ff ff 4b|4b ff ff b9) bl .* <.*\.long_branch\.g2>
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.*: (f5 ff ff 4b|4b ff ff f5) bl .* <g1>
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <f2>:
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.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
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.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
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.*: (4d ff ff 4b|4b ff ff 4d) bl .* <.*\.long_branch\.f1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (f9 ff ff 4b|4b ff ff f9) bl .* <f2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (45 ff ff 4b|4b ff ff 45) bl .* <.*\.long_branch\.g1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (1d 00 00 48|48 00 00 1d) bl .* <g2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (3d ff ff 4b|4b ff ff 3d) bl .* <.*\.plt_branch\.ext>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <g2>:
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.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
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.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
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.*: (cd ff ff 4b|4b ff ff cd) bl .* <f2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (11 ff ff 4b|4b ff ff 11) bl .* <.*\.long_branch\.f1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (f1 ff ff 4b|4b ff ff f1) bl .* <g2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (09 ff ff 4b|4b ff ff 09) bl .* <.*\.long_branch\.g1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <_start>:
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.*: (00 00 00 48|48 00 00 00) b .* <_start>
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Disassembly of section \.text\.ext:
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8000000000000000 <ext>:
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8000000000000000: (01 10 40 3c|3c 40 10 01) lis r2,4097
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8000000000000004: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
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8000000000000008: (00 00 00 60|60 00 00 00) nop
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800000000000000c: (20 00 80 4e|4e 80 00 20) blr
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