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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
78 lines
1.7 KiB
ArmAsm
78 lines
1.7 KiB
ArmAsm
# Hitachi H8 testcase 'or.l'
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# mach(): h8300h h8300s h8sx
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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start
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.if (sim_cpu == h8sx) ; 16-bit immediate is only available on sx.
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or_l_imm16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; or.l #xx:16,Rd
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or.l #0xaaaa, er0 ; Immediate 16-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xa5a5afaf er0 ; or result: a5a5a5a5 | aaaa
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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or_l_imm32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; or.l #xx:32,Rd
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or.l #0xaaaaaaaa, er0 ; Immediate 32-bit operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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or_l_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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;; fixme set ccr
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;; or.l Rs,Rd
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mov.l #0xaaaaaaaa, er1
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or.l er1, er0 ; Register operand
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;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0
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test_h_gr32 0xafafafaf er0 ; or result: a5a5a5a5 | aaaaaaaa
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test_h_gr32 0xaaaaaaaa er1 ; Make sure er1 is unchanged
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test_gr_a5a5 2 ; Make sure other general regs not disturbed
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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pass
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exit 0
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