mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
918 lines
17 KiB
ArmAsm
918 lines
17 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_loop_kill_dcr_01/se_loop_kill_dcr_01.dsp
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Include Files /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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include(std.inc)
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include(selfcheck.inc)
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include(symtable.inc)
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include(mmrs.inc)
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// Defines /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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#ifndef USER_CODE_SPACE
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#define USER_CODE_SPACE CODE_ADDR_1 //
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#endif
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000010
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#endif
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#ifndef ITABLE
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#define ITABLE CODE_ADDR_2 //
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#endif
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// RESET ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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RST_ISR :
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// Initialize Dregs
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INIT_R_REGS(0);
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// Initialize Pregs
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INIT_P_REGS(0);
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// Initialize ILBM Registers
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INIT_I_REGS(0);
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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// Initialize the Address of the Checkreg data segment
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// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
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CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
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// Setup User Stack
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LD32_LABEL(sp, USTACK);
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USP = SP;
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// Setup Kernel Stack
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LD32_LABEL(sp, KSTACK);
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// Setup Frame Pointer
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FP = SP;
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// Setup Event Vector Table
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LD32(p0, EVT0);
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LD32_LABEL(r0, EMU_ISR); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RST_ISR); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NMI_ISR); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, EXC_ISR); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWE_ISR); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, TMR_ISR); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
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[ P0 ++ ] = R0;
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// Setup the EVT_OVERRIDE MMR
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R0 = 0;
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LD32(p0, EVT_OVERRIDE);
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[ P0 ] = R0;
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// Setup Interrupt Mask
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R0 = -1;
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LD32(p0, IMASK);
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[ P0 ] = R0;
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// Return to Supervisor Code
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RAISE 15;
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NOP;
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LD32_LABEL(r0, USER_CODE);
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RETI = R0;
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EMU ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EMU_ISR :
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RTE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// NMI ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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NMI_ISR :
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RTN;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// EXC ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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EXC_ISR :
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RTX;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// HWE ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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HWE_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// TMR ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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TMR_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV7 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV7_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV8 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV8_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV9 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV9_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV10 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV10_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV11 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV11_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV12 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV12_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV13 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV13_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV14 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV14_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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/////////////////////////////////////////////////////////////////////////////
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///////////////////////// IGV15 ISR /////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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IGV15_ISR :
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P0 = 0x1 (Z);
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P1 = 0x2 (Z);
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P2 = 0x3 (Z);
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P3 = 0x4 (Z);
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P4 = 0x5 (Z);
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/////////////////////////////////////////////////////////////////////////////
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// Loop 0 (with Kill WB)
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/////////////////////////////////////////////////////////////////////////////
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// Kill Valid Dcr in WB
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LSETUP ( L0T , L0T ) LC0 = P0;
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EXCPT 0x5;
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L0T:R0 += 5;
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// Kill Valid Dcr in EX3
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LSETUP ( L1T , L1B ) LC0 = P0;
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EXCPT 0x5;
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L1T:R0 += 5;
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L1B:R1 += 4;
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// Kill Valid Dcr in EX2
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LSETUP ( L2T , L2B ) LC0 = P0;
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EXCPT 0x5;
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L2T:R0 += 5;
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R1 += 4;
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L2B:R2 += 3;
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// Kill Valid Dcr in EX1
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LSETUP ( L3T , L3B ) LC0 = P0;
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EXCPT 0x5;
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L3T:R0 += 5;
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R1 += 4;
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R2 += 3;
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L3B:R3 += 2;
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// Kill Valid Dcr in AC
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LSETUP ( L4T , L4B ) LC0 = P0;
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EXCPT 0x5;
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L4T:R0 += 5;
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R1 += 4;
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R2 += 3;
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R3 += 2;
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L4B:R4 += 1;
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// Kill Valid Dcr in WB, EX3
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LSETUP ( L5T , L5T ) LC0 = P1;
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EXCPT 0x5;
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L5T:R1 += 5;
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// Kill Valid Dcr in EX3, EX2
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LSETUP ( L6T , L6T ) LC0 = P1;
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EXCPT 0x5;
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NOP;
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L6T:R2 += 5;
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// Kill Valid Dcr in EX2, EX1
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LSETUP ( L7T , L7T ) LC0 = P1;
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EXCPT 0x5;
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NOP;
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NOP;
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L7T:R3 += 5;
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// Kill Valid Dcr in EX1, AC
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LSETUP ( L8T , L8T ) LC0 = P1;
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EXCPT 0x5;
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NOP;
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NOP;
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NOP;
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L8T:R4 += 5;
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// Kill Valid Dcr in WB, EX3, EX2
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LSETUP ( L9T , L9T ) LC0 = P2;
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EXCPT 0x5;
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L9T:R5 += 5;
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// Kill Valid Dcr in EX3, EX2, EX1
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LSETUP ( LAT , LAT ) LC0 = P2;
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EXCPT 0x5;
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NOP;
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LAT:
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R6 += 6;
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// Kill Valid Dcr in EX2, EX1, AC
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LSETUP ( LBT , LBT ) LC0 = P2;
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EXCPT 0x5;
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NOP;
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NOP;
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LBT:
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R5 += 5;
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// Kill Valid Dcr in WB, EX3, EX2, EX1
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LSETUP ( LCT , LCT ) LC0 = P3;
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EXCPT 0x5;
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LCT:
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R7 += 7;
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// Kill Valid Dcr in EX3, EX2, EX1, AC
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LSETUP ( LDT , LDT ) LC0 = P3;
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EXCPT 0x5;
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NOP;
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LDT:
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R0 += 7;
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// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
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LSETUP ( LET , LET ) LC0 = P4;
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EXCPT 0x5;
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LET:
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R1 += 1;
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// Kill Valid Dcr in WB, EX2
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LSETUP ( LFT , LFB ) LC0 = P1;
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LFT:
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EXCPT 0x5;
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LFB:
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R1 += 2;
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// Kill Valid Dcr in WB, EX1
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LSETUP ( LGT , LGB ) LC0 = P1;
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LGT:
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R2 += 3;
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EXCPT 0x5;
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LGB:
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R1 += 2;
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// Kill Valid Dcr in WB, AC
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LSETUP ( LHT , LHB ) LC0 = P1;
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LHT:
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R2 += 3;
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R3 += 4;
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EXCPT 0x5;
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LHB:
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R1 += 2;
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// Kill Valid Dcr in EX3, EX1
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LSETUP ( LIT , LIB ) LC0 = P1;
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EXCPT 0x5;
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LIT:
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R2 += 1;
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LIB:
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R1 += 2;
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|
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// Kill Valid Dcr in EX3, AC
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LSETUP ( LJT , LJB ) LC0 = P1;
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LJT:
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EXCPT 0x5;
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R2 += 1;
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LJB:
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R1 += 2;
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|
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// Kill Valid Dcr in EX2, AC
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LSETUP ( LKT , LKB ) LC0 = P1;
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EXCPT 0x5;
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NOP;
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LKT:
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R2 += 1;
|
|
LKB:
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R1 += 2;
|
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|
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// Kill Valid Dcr in WB, EX2, AC
|
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LSETUP ( LLT , LLB ) LC0 = P2;
|
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LLT:
|
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EXCPT 0x5;
|
|
LLB:
|
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R2 += 2;
|
|
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
// Loop 1 (with Kill WB)
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Kill Valid Dcr in WB
|
|
LSETUP ( M0T , M0T ) LC1 = P0;
|
|
EXCPT 0x5;
|
|
M0T:R0 += 5;
|
|
|
|
// Kill Valid Dcr in EX3
|
|
LSETUP ( M1T , M1B ) LC1 = P0;
|
|
EXCPT 0x5;
|
|
M1T:R0 += 5;
|
|
M1B:R1 += 4;
|
|
|
|
// Kill Valid Dcr in EX2
|
|
LSETUP ( M2T , M2B ) LC1 = P0;
|
|
EXCPT 0x5;
|
|
M2T:R0 += 5;
|
|
R1 += 4;
|
|
M2B:R2 += 3;
|
|
|
|
// Kill Valid Dcr in EX1
|
|
LSETUP ( M3T , M3B ) LC1 = P0;
|
|
EXCPT 0x5;
|
|
M3T:R0 += 5;
|
|
R1 += 4;
|
|
R2 += 3;
|
|
M3B:R3 += 2;
|
|
|
|
// Kill Valid Dcr in AC
|
|
LSETUP ( M4T , M4B ) LC1 = P0;
|
|
EXCPT 0x5;
|
|
M4T:R0 += 5;
|
|
R1 += 4;
|
|
R2 += 3;
|
|
R3 += 2;
|
|
M4B:R4 += 1;
|
|
|
|
// Kill Valid Dcr in WB, EX3
|
|
LSETUP ( M5T , M5T ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
M5T:R1 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2
|
|
LSETUP ( M6T , M6T ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
M6T:R2 += 5;
|
|
|
|
// Kill Valid Dcr in EX2, EX1
|
|
LSETUP ( M7T , M7T ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
NOP;
|
|
M7T:R3 += 5;
|
|
|
|
// Kill Valid Dcr in EX1, AC
|
|
LSETUP ( M8T , M8T ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
NOP;
|
|
NOP;
|
|
M8T:R4 += 5;
|
|
|
|
// Kill Valid Dcr in WB, EX3, EX2
|
|
LSETUP ( M9T , M9T ) LC1 = P2;
|
|
EXCPT 0x5;
|
|
M9T:R5 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1
|
|
LSETUP ( MAT , MAT ) LC1 = P2;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
MAT:
|
|
R6 += 6;
|
|
|
|
// Kill Valid Dcr in EX2, EX1, AC
|
|
LSETUP ( MBT , MBT ) LC1 = P2;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
NOP;
|
|
MBT:
|
|
R5 += 5;
|
|
|
|
// Kill Valid Dcr in WB, EX3, EX2, EX1
|
|
LSETUP ( MCT , MCT ) LC1 = P3;
|
|
EXCPT 0x5;
|
|
MCT:
|
|
R7 += 7;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1, AC
|
|
LSETUP ( MDT , MDT ) LC1 = P3;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
MDT:
|
|
R0 += 7;
|
|
|
|
// Kill Valid Dcr in WB, EX3, EX2, EX1, AC
|
|
LSETUP ( MET , MET ) LC1 = P4;
|
|
EXCPT 0x5;
|
|
MET:
|
|
R1 += 1;
|
|
|
|
// Kill Valid Dcr in WB, EX2
|
|
LSETUP ( MFT , MFB ) LC1 = P1;
|
|
MFT:
|
|
EXCPT 0x5;
|
|
MFB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in WB, EX1
|
|
LSETUP ( MGT , MGB ) LC1 = P1;
|
|
MGT:
|
|
R2 += 3;
|
|
EXCPT 0x5;
|
|
MGB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in WB, AC
|
|
LSETUP ( MHT , MHB ) LC1 = P1;
|
|
MHT:
|
|
R2 += 3;
|
|
R3 += 4;
|
|
EXCPT 0x5;
|
|
MHB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX3, EX1
|
|
LSETUP ( MIT , MIB ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
MIT:
|
|
R2 += 1;
|
|
MIB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX3, AC
|
|
LSETUP ( MJT , MJB ) LC1 = P1;
|
|
MJT:
|
|
EXCPT 0x5;
|
|
R2 += 1;
|
|
MJB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX2, AC
|
|
LSETUP ( MKT , MKB ) LC1 = P1;
|
|
EXCPT 0x5;
|
|
NOP;
|
|
MKT:
|
|
R2 += 1;
|
|
MKB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in WB, EX2, AC
|
|
LSETUP ( MLT , MLB ) LC1 = P2;
|
|
MLT:
|
|
EXCPT 0x5;
|
|
MLB:
|
|
R2 += 2;
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
// Loop 0 (with Kill EX3)
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
R0 = 1;
|
|
CC = R0;
|
|
|
|
// Kill %Valid Dcr in EX3
|
|
LSETUP ( N1T , N1T ) LC0 = P0;
|
|
IF CC JUMP 2;
|
|
N1T:R0 += 5;
|
|
|
|
// Kill Valid Dcr in EX2
|
|
LSETUP ( N2T , N2B ) LC0 = P0;
|
|
IF CC JUMP 2;
|
|
N2T:R0 += 5;
|
|
N2B:R2 += 3;
|
|
|
|
// Kill Valid Dcr in EX1
|
|
LSETUP ( N3T , N3B ) LC0 = P0;
|
|
IF CC JUMP 2;
|
|
N3T:R0 += 5;
|
|
R2 += 3;
|
|
N3B:R3 += 2;
|
|
|
|
// Kill Valid Dcr in AC
|
|
LSETUP ( N4T , N4B ) LC0 = P0;
|
|
IF CC JUMP 2;
|
|
N4T:R0 += 5;
|
|
R2 += 3;
|
|
R3 += 2;
|
|
N4B:R4 += 1;
|
|
|
|
// Kill Valid Dcr in EX3, EX2
|
|
LSETUP ( N6T , N6T ) LC0 = P1;
|
|
IF CC JUMP 2;
|
|
N6T:R2 += 5;
|
|
|
|
// Kill Valid Dcr in EX2, EX1
|
|
LSETUP ( N7T , N7T ) LC0 = P1;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
N7T:R3 += 5;
|
|
|
|
// Kill Valid Dcr in EX1, AC
|
|
LSETUP ( N8T , N8T ) LC0 = P1;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
NOP;
|
|
N8T:R4 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1
|
|
LSETUP ( NAT , NAT ) LC0 = P2;
|
|
IF CC JUMP 2;
|
|
NAT:
|
|
R6 += 6;
|
|
|
|
// Kill Valid Dcr in EX2, EX1, AC
|
|
LSETUP ( NBT , NBT ) LC0 = P2;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
NBT:
|
|
R5 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1, AC
|
|
LSETUP ( NDT , NDT ) LC0 = P3;
|
|
IF CC JUMP 2;
|
|
NDT:
|
|
R0 += 7;
|
|
|
|
// Kill Valid Dcr in EX3, EX1
|
|
LSETUP ( NIT , NIB ) LC0 = P1;
|
|
NIT:
|
|
IF CC JUMP 2;
|
|
NIB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX3, AC
|
|
LSETUP ( NJT , NJB ) LC0 = P1;
|
|
NJT:
|
|
R2 += 1;
|
|
IF CC JUMP 2;
|
|
NJB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX2, AC
|
|
LSETUP ( NKT , NKB ) LC0 = P1;
|
|
IF CC JUMP 2;
|
|
NKT:
|
|
R2 += 1;
|
|
NKB:
|
|
R1 += 2;
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
// Loop 1 (with Kill EX3)
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Kill %Valid Dcr in EX3
|
|
LSETUP ( O1T , O1T ) LC1 = P0;
|
|
IF CC JUMP 2;
|
|
O1T:R0 += 5;
|
|
|
|
// Kill Valid Dcr in EX2
|
|
LSETUP ( O2T , O2B ) LC1 = P0;
|
|
IF CC JUMP 2;
|
|
O2T:R0 += 5;
|
|
O2B:R2 += 3;
|
|
|
|
// Kill Valid Dcr in EX1
|
|
LSETUP ( O3T , O3B ) LC1 = P0;
|
|
IF CC JUMP 2;
|
|
O3T:R0 += 5;
|
|
R2 += 3;
|
|
O3B:R3 += 2;
|
|
|
|
// Kill Valid Dcr in AC
|
|
LSETUP ( O4T , O4B ) LC1 = P0;
|
|
IF CC JUMP 2;
|
|
O4T:R0 += 5;
|
|
R2 += 3;
|
|
R3 += 2;
|
|
O4B:R4 += 1;
|
|
|
|
// Kill Valid Dcr in EX3, EX2
|
|
LSETUP ( O6T , O6T ) LC1 = P1;
|
|
IF CC JUMP 2;
|
|
O6T:R2 += 5;
|
|
|
|
// Kill Valid Dcr in EX2, EX1
|
|
LSETUP ( O7T , O7T ) LC1 = P1;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
O7T:R3 += 5;
|
|
|
|
// Kill Valid Dcr in EX1, AC
|
|
LSETUP ( O8T , O8T ) LC1 = P1;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
NOP;
|
|
O8T:R4 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1
|
|
LSETUP ( OAT , OAT ) LC1 = P2;
|
|
IF CC JUMP 2;
|
|
OAT:
|
|
R6 += 6;
|
|
|
|
// Kill Valid Dcr in EX2, EX1, AC
|
|
LSETUP ( OBT , OBT ) LC1 = P2;
|
|
IF CC JUMP 2;
|
|
NOP;
|
|
OBT:
|
|
R5 += 5;
|
|
|
|
// Kill Valid Dcr in EX3, EX2, EX1, AC
|
|
LSETUP ( ODT , ODT ) LC1 = P3;
|
|
IF CC JUMP 2;
|
|
ODT:
|
|
R0 += 7;
|
|
|
|
// Kill Valid Dcr in EX3, EX1
|
|
LSETUP ( OIT , OIB ) LC1 = P1;
|
|
OIT:
|
|
IF CC JUMP 2;
|
|
OIB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX3, AC
|
|
LSETUP ( OJT , OJB ) LC1 = P1;
|
|
OJT:
|
|
R2 += 1;
|
|
IF CC JUMP 2;
|
|
OJB:
|
|
R1 += 2;
|
|
|
|
// Kill Valid Dcr in EX2, AC
|
|
LSETUP ( OKT , OKB ) LC1 = P1;
|
|
IF CC JUMP 2;
|
|
OKT:
|
|
R2 += 1;
|
|
OKB:
|
|
R1 += 2;
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
// Loop 0 (with Kill AC)
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Kill Valid Dcr in AC
|
|
LSETUP ( P4T , P4T ) LC0 = P0;
|
|
JUMP.S 2;
|
|
P4T:R0 += 5;
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
// Loop 1 (with Kill AC)
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Kill Valid Dcr in AC
|
|
LSETUP ( Q4T , Q4T ) LC1 = P0;
|
|
JUMP.S 2;
|
|
Q4T:R0 += 5;
|
|
|
|
NOP;
|
|
NOP;
|
|
RTI;
|
|
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
.dw 0xFFFF
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
///////////////////////// USER CODE /////////////////////////////
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
USER_CODE :
|
|
|
|
NOP;
|
|
NOP;
|
|
NOP;
|
|
NOP;
|
|
dbg_pass; // Call Endtest Macro
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
///////////////////////// DATA MEMRORY /////////////////////////////
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
|
|
.section MEM_DATA_ADDR_1 //.data 0x00F00100,"aw"
|
|
.dd 0xdeadbeef;
|
|
.section MEM_(DATA_ADDR_1 + 0x100) //.data 0x00F00200,"aw"
|
|
.dd 0x01010101; //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
|
|
.dd 0x02020202;
|
|
.dd 0x03030303;
|
|
.dd 0x04040404;
|
|
|
|
// Define Kernal Stack
|
|
.data
|
|
.space (STACKSIZE); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
|
|
KSTACK :
|
|
|
|
.space (STACKSIZE);
|
|
USTACK :
|
|
|
|
/////////////////////////////////////////////////////////////////////////////
|
|
///////////////////////// END OF TEST /////////////////////////////
|
|
/////////////////////////////////////////////////////////////////////////////
|