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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
186 lines
6.2 KiB
ArmAsm
186 lines
6.2 KiB
ArmAsm
# Check that VS in ASTAT is set with add/sub insns (and not just V)
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# mach: bfin
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#include "test.h"
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.include "testutils.inc"
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start
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dmm32 ASTAT, (0x2810c010 | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
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imm32 R0, 0x27f3a149;
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imm32 R3, 0x3cae7c58;
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imm32 R4, 0x33c97634;
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R3.H = R0.L - R4.H (NS);
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checkreg R3, 0x6d807c58;
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checkreg ASTAT, (0x2810c010 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x64c00680 | _AQ | _AC0_COPY);
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imm32 R1, 0x1b7b025c;
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imm32 R5, 0x1ba46ce6;
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R5.L = R5.L + R1.H (NS);
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checkreg R5, 0x1ba48861;
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checkreg ASTAT, (0x64c00680 | _VS | _V | _AQ | _V_COPY | _AN);
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dmm32 ASTAT, (0x68b04200 | _AV1S | _AV0 | _AC0 | _AQ | _AN);
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imm32 R3, 0x4b91870f;
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imm32 R6, 0x5972bae0;
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imm32 R7, 0x31f7dfb7;
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R7.H = R6.L + R3.L (S);
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checkreg R7, 0x8000dfb7;
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checkreg ASTAT, (0x68b04200 | _VS | _V | _AV1S | _AV0 | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
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dmm32 ASTAT, (0x78208e90 | _CC | _AN);
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imm32 R3, 0x40b63bc7;
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imm32 R5, 0x49c89df9;
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R3.H = R5.L - R3.H (NS);
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checkreg R3, 0x5d433bc7;
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checkreg ASTAT, (0x78208e90 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x00904680 | _AV1S | _AV1 | _AV0 | _AC1 | _AQ | _AZ);
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imm32 R2, 0x23a2c115;
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imm32 R4, 0x6977581e;
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imm32 R6, 0x41900942;
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R4.L = R2.L - R6.H (NS);
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checkreg R4, 0x69777f85;
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checkreg ASTAT, (0x00904680 | _VS | _V | _AV1S | _AV1 | _AV0 | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x78d08210 | _V | _AV1S | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN | _AZ);
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imm32 R0, 0x4317139e;
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imm32 R1, 0x49ed40d6;
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R0.L = R1.L + R0.H (NS);
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checkreg R0, 0x431783ed;
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checkreg ASTAT, (0x78d08210 | _VS | _V | _AV1S | _AC1 | _V_COPY | _AN);
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dmm32 ASTAT, (0x58d00e10 | _AV1 | _AQ | _CC);
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imm32 R0, 0x09ea77a2;
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imm32 R1, 0x6ccd0b05;
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imm32 R2, 0x761c63af;
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R1.H = R0.L + R2.H (NS);
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checkreg R1, 0xedbe0b05;
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checkreg ASTAT, (0x58d00e10 | _VS | _V | _AV1 | _AQ | _CC | _V_COPY | _AN);
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dmm32 ASTAT, (0x30c08000 | _AC0 | _AQ | _AC0_COPY);
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imm32 R4, 0x36d243cb;
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imm32 R5, 0xcd127add;
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R4.H = R5.L + R4.L (NS);
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checkreg R4, 0xbea843cb;
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checkreg ASTAT, (0x30c08000 | _VS | _V | _AQ | _V_COPY | _AN);
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dmm32 ASTAT, (0x74108400 | _V | _AV1 | _AC1 | _AC0 | _AC0_COPY);
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imm32 R0, 0x4e1893ea;
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imm32 R1, 0x13cf5cc8;
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imm32 R3, 0x7441949e;
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R1.L = R0.L - R3.H (NS);
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checkreg R1, 0x13cf1fa9;
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checkreg ASTAT, (0x74108400 | _VS | _V | _AV1 | _AC1 | _AC0 | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x7420ce10 | _AV1S | _AV1 | _AV0S | _AC1 | _AQ | _AC0_COPY | _AN | _AZ);
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imm32 R4, 0x532c8fb1;
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imm32 R6, 0x582420d2;
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R6.H = R4.L - R4.H (NS);
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checkreg R6, 0x3c8520d2;
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checkreg ASTAT, (0x7420ce10 | _VS | _V | _AV1S | _AV1 | _AV0S | _AC1 | _AC0 | _AQ | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x74704010 | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY);
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imm32 R3, 0x6f6a7429;
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imm32 R5, 0x2ea5c47e;
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R5.H = R5.L - R3.H (NS);
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checkreg R5, 0x5514c47e;
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checkreg ASTAT, (0x74704010 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x0ce08490 | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _AZ);
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imm32 R1, 0xfd18a0b0;
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imm32 R4, 0x259e2151;
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R4.L = R1.L - R4.H (NS);
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checkreg R4, 0x259e7b12;
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checkreg ASTAT, (0x0ce08490 | _VS | _V | _AV1S | _AV0S | _AC1 | _AC0 | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x54b08810 | _V | _AV1S | _AV0S | _AC0_COPY | _AN);
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imm32 R3, 0x7a763675;
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imm32 R6, 0x23c4a335;
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R3.L = R6.L + R6.L (NS);
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checkreg R3, 0x7a76466a;
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checkreg ASTAT, (0x54b08810 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x70f0c080 | _AV1S | _AV0S | _AC0);
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imm32 R4, 0x55fab7e4;
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imm32 R5, 0x7dbd9b06;
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R5.H = R5.L - R4.H (S);
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checkreg R5, 0x80009b06;
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checkreg ASTAT, (0x70f0c080 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
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dmm32 ASTAT, (0x5ce04680 | _AV0 | _AC0 | _V_COPY | _AC0_COPY | _AN);
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imm32 R0, 0x19cacbdb;
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imm32 R2, 0x151cb293;
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imm32 R4, 0x571c351a;
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R0.H = R4.L - R2.L (S);
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checkreg R0, 0x7fffcbdb;
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checkreg ASTAT, (0x5ce04680 | _VS | _V | _AV0 | _V_COPY);
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dmm32 ASTAT, (0x0c604a00 | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AZ);
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imm32 R3, 0x5432c45d;
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imm32 R6, 0x62519952;
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R3.L = R6.L + R6.L (S);
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checkreg R3, 0x54328000;
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checkreg ASTAT, (0x0c604a00 | _VS | _V | _AV1S | _AV0S | _AC0 | _V_COPY | _AC0_COPY | _AN);
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dmm32 ASTAT, (0x58708c90 | _AV0 | _AC1 | _AQ | _CC | _AC0_COPY | _AN | _AZ);
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imm32 R0, 0x1f3f3c0e;
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imm32 R4, 0x5fae58d2;
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R0.H = R0.L + R4.L (NS);
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checkreg R0, 0x94e03c0e;
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checkreg ASTAT, (0x58708c90 | _VS | _V | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AN);
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dmm32 ASTAT, (0x34b00a00 | _V | _AV1S | _AC1 | _CC | _V_COPY | _AZ);
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imm32 R3, 0x6ea226dc;
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imm32 R4, 0x045c6d64;
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imm32 R7, 0x7e599a25;
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R7.L = R3.L + R4.L (NS);
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checkreg R7, 0x7e599440;
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checkreg ASTAT, (0x34b00a00 | _VS | _V | _AV1S | _AC1 | _CC | _V_COPY | _AN);
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dmm32 ASTAT, (0x40a0c010 | _AV1S | _AC0);
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imm32 R2, 0x641501ef;
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imm32 R7, 0x3acb49aa;
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R2.H = R7.L + R7.H (NS);
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checkreg R2, 0x847501ef;
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checkreg ASTAT, (0x40a0c010 | _VS | _V | _AV1S | _V_COPY | _AN);
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dmm32 ASTAT, (0x78f04090 | _AV1S | _AC1 | _AQ | _CC | _AZ);
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imm32 R2, 0x65681fdf;
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imm32 R3, 0x5fffe0d3;
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imm32 R5, 0x37df99cd;
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R2.H = R5.L - R3.H (NS);
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checkreg R2, 0x39ce1fdf;
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checkreg ASTAT, (0x78f04090 | _VS | _V | _AV1S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x0cc04e10 | _AV1S | _AQ | _CC);
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imm32 R3, 0x571977df;
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imm32 R4, 0x029671d0;
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R3.L = R4.L + R3.H (NS);
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checkreg R3, 0x5719c8e9;
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checkreg ASTAT, (0x0cc04e10 | _VS | _V | _AV1S | _AQ | _CC | _V_COPY | _AN);
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dmm32 ASTAT, (0x00104880 | _AV0S | _AC1 | _AC0 | _AQ | _CC | _AC0_COPY | _AN);
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imm32 R0, 0x4c98aa07;
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imm32 R4, 0x5e9da59f;
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R4.H = R0.L + R0.L (S);
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checkreg R4, 0x8000a59f;
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checkreg ASTAT, (0x00104880 | _VS | _V | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
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dmm32 ASTAT, (0x08008c00 | _AV1S | _AV0S | _AV0 | _CC | _AC0_COPY);
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imm32 R4, 0x58ee2400;
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imm32 R6, 0x2e97af3e;
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R4.L = R6.L + R6.L (NS);
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checkreg R4, 0x58ee5e7c;
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checkreg ASTAT, (0x08008c00 | _VS | _V | _AV1S | _AV0S | _AV0 | _AC0 | _CC | _V_COPY | _AC0_COPY);
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dmm32 ASTAT, (0x2ce0c290 | _V | _AV1S | _AV0S | _AC1 | _AC0 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
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imm32 R2, 0x2d467e64;
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imm32 R6, 0x31aeb601;
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imm32 R7, 0x1523a746;
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R7.L = R2.L - R6.L (S);
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checkreg R7, 0x15237fff;
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checkreg ASTAT, (0x2ce0c290 | _VS | _V | _AV1S | _AV0S | _AC1 | _AQ | _CC | _V_COPY);
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pass
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