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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
169 lines
2.6 KiB
ArmAsm
169 lines
2.6 KiB
ArmAsm
//Original:/testcases/core/c_ldimmhalf_lz_ibml/c_ldimmhalf_lz_ibml.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: ldimmhalf lz ibml
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I0 = 0x2001 (Z);
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I1 = 0x2003 (Z);
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I2 = 0x2005 (Z);
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I3 = 0x2007 (Z);
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L0 = 0x2009 (Z);
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L1 = 0x200b (Z);
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L2 = 0x200d (Z);
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L3 = 0x200f (Z);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x00002001;
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CHECKREG r1, 0x00002003;
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CHECKREG r2, 0x00002005;
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CHECKREG r3, 0x00002007;
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CHECKREG r4, 0x00002009;
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CHECKREG r5, 0x0000200b;
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CHECKREG r6, 0x0000200d;
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CHECKREG r7, 0x0000200f;
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I0 = 0x0111 (Z);
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I1 = 0x1111 (Z);
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I2 = 0x2222 (Z);
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I3 = 0x3333 (Z);
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L0 = 0x4444 (Z);
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L1 = 0x5555 (Z);
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L2 = 0x6666 (Z);
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L3 = 0x7777 (Z);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x00000111;
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CHECKREG r1, 0x00001111;
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CHECKREG r2, 0x00002222;
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CHECKREG r3, 0x00003333;
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CHECKREG r4, 0x00004444;
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CHECKREG r5, 0x00005555;
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CHECKREG r6, 0x00006666;
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CHECKREG r7, 0x00007777;
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I0 = 0x8888 (Z);
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I1 = 0x9aaa (Z);
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I2 = 0xabbb (Z);
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I3 = 0xbccc (Z);
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L0 = 0xcddd (Z);
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L1 = 0xdeee (Z);
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L2 = 0xefff (Z);
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L3 = 0xf111 (Z);
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R0 = I0;
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R1 = I1;
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R2 = I2;
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R3 = I3;
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R4 = L0;
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R5 = L1;
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R6 = L2;
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R7 = L3;
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CHECKREG r0, 0x00008888;
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CHECKREG r1, 0x00009aaa;
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CHECKREG r2, 0x0000abbb;
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CHECKREG r3, 0x0000bccc;
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CHECKREG r4, 0x0000cddd;
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CHECKREG r5, 0x0000deee;
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CHECKREG r6, 0x0000efff;
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CHECKREG r7, 0x0000f111;
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B0 = 0x3001 (Z);
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B1 = 0x3003 (Z);
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B2 = 0x3005 (Z);
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B3 = 0x3007 (Z);
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M0 = 0x3009 (Z);
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M1 = 0x300b (Z);
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M2 = 0x300d (Z);
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M3 = 0x300f (Z);
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00003001;
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CHECKREG r1, 0x00003003;
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CHECKREG r2, 0x00003005;
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CHECKREG r3, 0x00003007;
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CHECKREG r4, 0x00003009;
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CHECKREG r5, 0x0000300B;
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CHECKREG r6, 0x0000300d;
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CHECKREG r7, 0x0000300f;
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B0 = 0x0110 (Z);
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B1 = 0x1110 (Z);
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B2 = 0x2220 (Z);
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B3 = 0x3330 (Z);
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M0 = 0x4440 (Z);
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M1 = 0x5550 (Z);
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M2 = 0x6660 (Z);
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M3 = 0x7770 (Z);
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x00000110;
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CHECKREG r1, 0x00001110;
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CHECKREG r2, 0x00002220;
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CHECKREG r3, 0x00003330;
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CHECKREG r4, 0x00004440;
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CHECKREG r5, 0x00005550;
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CHECKREG r6, 0x00006660;
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CHECKREG r7, 0x00007770;
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B0 = 0xf880 (Z);
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B1 = 0xfaa0 (Z);
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B2 = 0xfbb0 (Z);
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B3 = 0xfcc0 (Z);
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M0 = 0xfdd0 (Z);
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M1 = 0xfee0 (Z);
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M2 = 0xfff0 (Z);
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M3 = 0xf110 (Z);
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R0 = B0;
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R1 = B1;
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R2 = B2;
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R3 = B3;
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R4 = M0;
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R5 = M1;
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R6 = M2;
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R7 = M3;
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CHECKREG r0, 0x0000f880;
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CHECKREG r1, 0x0000faa0;
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CHECKREG r2, 0x0000fbb0;
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CHECKREG r3, 0x0000fcc0;
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CHECKREG r4, 0x0000fdd0;
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CHECKREG r5, 0x0000fee0;
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CHECKREG r6, 0x0000fff0;
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CHECKREG r7, 0x0000f110;
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pass
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