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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
150 lines
3.3 KiB
ArmAsm
150 lines
3.3 KiB
ArmAsm
//Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
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# mach: bfin
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.include "testutils.inc"
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start
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// Spec Reference: dsp32shiftimm ashift: mix
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imm32 r4, 0x00000000;
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imm32 r5, 0x00000000;
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imm32 r6, 0x00000000;
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imm32 r7, 0x00000000;
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// Ashift : positive data, count (+)=left (half reg)
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imm32 r0, 0x00010001;
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imm32 r1, 1;
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imm32 r2, 0x00020002;
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imm32 r3, 2;
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R4.H = R0.H << 1;
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R4.L = R0.L << 1; /* r4 = 0x00020002 */
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R5.H = R2.H << 2;
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R5.L = R2.L << 2; /* r5 = 0x00080008 */
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R6 = R0 << 1 (V); /* r6 = 0x00020002 */
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R7 = R2 << 2 (V); /* r7 = 0x00080008 */
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CHECKREG r4, 0x00020002;
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CHECKREG r5, 0x00080008;
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CHECKREG r6, 0x00020002;
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CHECKREG r7, 0x00080008;
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imm32 r1, 3;
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imm32 r3, 4;
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R6 = R0 << 3; /* r6 = 0x00080010 */
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R7 = R2 << 4;
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CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
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CHECKREG r7, 0x00200020;
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A0 = 0;
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A0.L = R0.L;
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A0.H = R0.H;
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A0 = A0 << 3; /* a0 = 0x00080008 */
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R5 = A0.w; /* r5 = 0x00080008 */
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CHECKREG r5, 0x00080008;
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imm32 r4, 0x30000003;
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imm32 r1, 1;
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R5 = R4 << 1; /* r5 = 0x60000006 */
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imm32 r1, 2;
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R6 = ASHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
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CHECKREG r5, 0x60000006;
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CHECKREG r6, 0xc000000c;
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// Ashift : count (-)=right (half reg)
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imm32 r0, 0x10001000;
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imm32 r1, -1;
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imm32 r2, 0x10001000;
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imm32 r3, -2;
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R4.H = R0.H >>> 1;
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R4.L = R0.L >>> 1; /* r4 = 0x08000800 */
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R5.H = R2.H >>> 2;
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R5.L = R2.L >>> 2; /* r4 = 0x04000400 */
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R6 = R0 >>> 1 (V); /* r4 = 0x08000800 */
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R7 = R2 >>> 2 (V); /* r4 = 0x04000400 */
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CHECKREG r4, 0x08000800;
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CHECKREG r5, 0x04000400;
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CHECKREG r6, 0x08000800;
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CHECKREG r7, 0x04000400;
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// Ashift : (full reg)
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imm32 r1, -3;
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imm32 r3, -4;
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R6 = R0 >>> 3; /* r6 = 0x02000200 */
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R7 = R2 >>> 4; /* r7 = 0x01000100 */
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CHECKREG r6, 0x02000200;
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CHECKREG r7, 0x01000100;
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// NEGATIVE
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// Ashift : NEGATIVE data, count (+)=left (half reg)
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imm32 r0, 0xc00f800f;
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imm32 r1, 1;
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imm32 r2, 0xe00fe00f;
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imm32 r3, 2;
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R4.H = R0.H << 1;
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R4.L = R0.L << 1 (S); /* r4 = 0x801e801e */
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R5.H = R2.H << 2;
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R5.L = R2.L << 2; /* r4 = 0x803c803c */
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CHECKREG r4, 0x801e8000;
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CHECKREG r5, 0x803c803c;
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imm32 r0, 0xc80fe00f;
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imm32 r2, 0xe40fe00f;
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imm32 r1, 4;
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imm32 r3, 5;
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R6 = R0 << 4; /* r6 = 0x80fe00f0 */
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R7 = R2 << 5; /* r7 = 0x81fc01e0 */
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CHECKREG r6, 0x80fe00f0;
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CHECKREG r7, 0x81fc01e0;
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imm32 r0, 0xf80fe00f;
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imm32 r2, 0xfc0fe00f;
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R6 = R0 << 4 (S); /* r6 = 0x80fe00f0 */
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R7 = R2 << 5 (S); /* r7 = 0x81fc01e0 */
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CHECKREG r6, 0x80fe00f0;
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CHECKREG r7, 0x81fc01e0;
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imm32 r0, 0xc80fe00f;
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imm32 r2, 0xe40fe00f;
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R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */
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R7 = R2 << 5 (S); /* r7 = 0x80000000 */
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0x80000000;
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imm32 r0, 0xFFFFFFF4;
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imm32 r2, 0xFFF00001;
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R6 = R0 << 31 (S); /* r6 = 0x80000000 */
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R7 = R2 << 31 (S); /* r7 = 0x80000000 */
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CHECKREG r6, 0x80000000;
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CHECKREG r7, 0x80000000;
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// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
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imm32 r0, 0x80f080f0;
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imm32 r1, -1;
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imm32 r2, 0x80f080f0;
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imm32 r3, -2;
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R4.H = R0.H >>> 1;
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R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */
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R5.H = R2.H >>> 2;
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R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */
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CHECKREG r4, 0xc078c078;
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CHECKREG r5, 0xe03ce03c;
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R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */
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R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */
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CHECKREG r6, 0xc078c078;
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CHECKREG r7, 0xe03ce03c;
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imm32 r1, -3;
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imm32 r3, -4;
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R6 = R0 >>> 3; /* r6 = 0xf01e101e */
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R7 = R2 >>> 4; /* r7 = 0xf80f080f */
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CHECKREG r6, 0xf01e101e;
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CHECKREG r7, 0xf80f080f;
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pass
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