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06c441ccef
2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
89 lines
3.3 KiB
C
89 lines
3.3 KiB
C
/*> cp1.h <*/
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/* MIPS Simulator FPU (CoProcessor 1) definitions.
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Copyright (C) 1997-2022 Free Software Foundation, Inc.
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Derived from sim-main.h contributed by Cygnus Solutions,
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modified substantially by Ed Satterthwaite of Broadcom Corporation
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(SiByte).
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CP1_H
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#define CP1_H
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/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
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in CPU state (struct sim_cpu), and for FPU functions. */
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#define fcsr_FCC_mask (0xFE800000)
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#define fcsr_FCC_shift (23)
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#define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc)))
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#define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
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#define fcsr_ZERO_mask (0x007C0000)
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#define fcsr_CAUSE_mask (0x0003F000)
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#define fcsr_CAUSE_shift (12)
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#define fcsr_ENABLES_mask (0x00000F80)
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#define fcsr_ENABLES_shift (7)
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#define fcsr_FLAGS_mask (0x0000007C)
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#define fcsr_FLAGS_shift (2)
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#define fcsr_RM_mask (0x00000003)
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#define fcsr_RM_shift (0)
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/* FCSR bits for IEEE754-2008 compliance. */
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#define fcsr_NAN2008_mask (0x00040000)
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#define fcsr_NAN2008_shift (18)
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#define fcsr_ABS2008_mask (0x00080000)
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#define fcsr_ABS2008_shift (19)
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#define fenr_FS (0x00000004)
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/* Macros to update and retrieve the FCSR condition-code bits. This
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is complicated by the fact that there is a hole in the index range
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of the bits within the FCSR register. (Note that the number of bits
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visible depends on the ISA in use, but that is handled elsewhere.) */
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#define SETFCC(cc,v) \
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do { \
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(FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \
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} while (0)
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#define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0)
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/* Read flush-to-zero bit (not right-justified). */
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#define GETFS() ((int)(FCSR & fcsr_FS))
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/* FCSR flag bits definitions and access macros. */
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#define IR 0 /* I: Inexact Result */
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#define UF 1 /* U: UnderFlow */
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#define OF 2 /* O: OverFlow */
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#define DZ 3 /* Z: Division by Zero */
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#define IO 4 /* V: Invalid Operation */
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#define UO 5 /* E: Unimplemented Operation (CAUSE field only) */
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#define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift))
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#define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift))
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#define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift))
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/* Rounding mode bit definitions and access macros. */
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#define FP_RM_NEAREST 0 /* Round to nearest (Round). */
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#define FP_RM_TOZERO 1 /* Round to zero (Trunc). */
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#define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */
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#define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */
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#define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask)
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#endif /* CP1_H */
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