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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
312 lines
5.9 KiB
ArmAsm
312 lines
5.9 KiB
ArmAsm
# sh testcase for loop control
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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start
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loop1:
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set_grs_a5a5
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ldrs Loop1_start0+8
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ldre Loop1_start0+4
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setrc #5
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Loop1_start0:
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add #1, r1 ! Before loop
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# Loop should execute one instruction five times.
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Loop1_begin:
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add #1, r1 ! Within loop
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Loop1_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
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assertreg 0xa5a5a5a5+8, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop2:
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set_grs_a5a5
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ldrs Loop2_start0+6
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ldre Loop2_start0+4
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setrc #5
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Loop2_start0:
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add #1, r1 ! Before loop
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# Loop should execute two instructions five times.
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Loop2_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop2_end:
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add #3, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 14 (ten in loop, three after, one before)
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assertreg 0xa5a5a5a5+14, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop3:
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set_grs_a5a5
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ldrs Loop3_start0+4
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ldre Loop3_start0+4
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setrc #5
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Loop3_start0:
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add #1, r1 ! Before loop
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# Loop should execute three instructions five times.
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Loop3_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop3_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
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assertreg 0xa5a5a5a5+18, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop4:
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set_grs_a5a5
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ldrs Loop4_begin
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ldre Loop4_last3+4
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setrc #5
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add #1, r1 ! Before loop
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# Loop should execute four instructions five times.
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Loop4_begin:
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Loop4_last3:
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add #1, r1 ! Within loop
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Loop4_last2:
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add #1, r1 ! Within loop
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Loop4_last1:
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add #1, r1 ! Within loop
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Loop4_last:
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add #1, r1 ! Within loop
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Loop4_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 23 (20 in loop, two after, one before)
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assertreg 0xa5a5a5a5+23, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop5:
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set_grs_a5a5
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ldrs Loop5_begin
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ldre Loop5_last3+4
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setrc #5
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add #1, r1 ! Before loop
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# Loop should execute five instructions five times.
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Loop5_begin:
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add #1, r1 ! Within loop
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Loop5_last3:
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add #1, r1 ! Within loop
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Loop5_last2:
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add #1, r1 ! Within loop
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Loop5_last1:
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add #1, r1 ! Within loop
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Loop5_last:
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add #1, r1 ! Within loop
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Loop5_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 28 (25 in loop, two after, one before)
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assertreg 0xa5a5a5a5+28, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loopn:
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set_grs_a5a5
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ldrs Loopn_begin
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ldre Loopn_last3+4
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setrc #5
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add #1, r1 ! Before loop
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# Loop should execute n instructions five times.
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Loopn_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loopn_last3:
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add #1, r1 ! Within loop
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Loopn_last2:
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add #1, r1 ! Within loop
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Loopn_last1:
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add #1, r1 ! Within loop
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Loopn_last:
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add #1, r1 ! Within loop
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Loopn_end:
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add #3, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 64 (60 in loop, three after, one before)
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assertreg 0xa5a5a5a5+64, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop1e:
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set_grs_a5a5
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ldrs Loop1e_begin
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ldre Loop1e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute one instruction five times.
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Loop1e_begin:
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Loop1e_last:
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add #1, r1 ! Within loop
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Loop1e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 8 (five in loop, two after, one before)
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assertreg 0xa5a5a5a5+8, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop2e:
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set_grs_a5a5
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ldrs Loop2e_begin
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ldre Loop2e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute two instructions five times.
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Loop2e_begin:
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add #1, r1 ! Within loop
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Loop2e_last:
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add #1, r1 ! Within loop
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Loop2e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 13 (ten in loop, two after, one before)
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assertreg 0xa5a5a5a5+13, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop3e:
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set_grs_a5a5
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ldrs Loop3e_begin
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ldre Loop3e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute three instructions five times.
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Loop3e_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop3e_last:
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add #1, r1 ! Within loop
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Loop3e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 18 (fifteen in loop, two after, one before)
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assertreg 0xa5a5a5a5+18, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop4e:
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set_grs_a5a5
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ldrs Loop4e_begin
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ldre Loop4e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute four instructions five times.
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Loop4e_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop4e_last:
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add #1, r1 ! Within loop
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Loop4e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 23 (twenty in loop, two after, one before)
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assertreg 0xa5a5a5a5+23, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop5e:
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set_grs_a5a5
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ldrs Loop5e_begin
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ldre Loop5e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute five instructions five times.
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Loop5e_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop5e_last:
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add #1, r1 ! Within loop
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Loop5e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 28 (twenty five in loop, two after, one before)
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assertreg 0xa5a5a5a5+28, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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loop_n_e:
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set_grs_a5a5
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ldrs Loop_n_e_begin
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ldre Loop_n_e_last
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ldrc #5
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add #1, r1 ! Before loop
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# Loop should execute n instructions five times.
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Loop_n_e_begin:
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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add #1, r1 ! Within loop
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Loop_n_e_last:
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add #1, r1 ! Within loop
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Loop_n_e_end:
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add #2, r1 ! After loop
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# r1 = 0xa5a5a5a5 + 48 (forty five in loop, two after, one before)
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assertreg 0xa5a5a5a5+48, r1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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pass
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exit 0
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