binutils-gdb/sim/testsuite/v850/bins.cgs
Jeff Law 49fffa58f7 Fix "bins" simulation for v850e3v5
I've been carrying this for a few years.   One test in the GCC testsuite is
failing due to a bug in the handling of the v850e3v5 instruction "bins".

When the "bins" instruction specifies a 32bit bitfield size, the simulator
exhibits undefined behavior by trying to shift a 32 bit quantity by 32 bits.
In the case of a 32 bit shift, we know what the resultant mask should be.  So
we can just set it.

That seemed better than using 1UL for the constant (on a 32bit host unsigned
long might still just be 32 bits) or needlessly forcing everything to
long long types.

Thankfully the case where this shows up is only bins <src>, 0, 32, <dest>
which would normally be encoded as a simple move.

	* testsuite/v850/allinsns.exp: Add v850e3v5.
	* testsuite/v850/bins.cgs: New test.
	* v850/simops.c (v850_bins): Avoid undefined behavior on left shift.
2022-04-06 11:06:53 -04:00

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# v850 bins
# mach: v850e3v5
# as: -mv850e3v5
.include "testutils.inc"
seti 0x7fff, r10
seti 0x0, r11
bins r10, 0, 32, r11
reg r11, 0x7fff
pass