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7b2ec4e46f
Set the mach to the right value all the time, and update xfail to say the test fails on all targets. WIth multitarget testing, the idea of target here doesn't make much sense.
623 lines
12 KiB
ArmAsm
623 lines
12 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_illegalcombination/se_illegalcombination.dsp
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// Description: Multi-issue Illegal Combinations
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# mach: bfin
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# sim: --environment operating
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# xfail: "missing a few checks; hardware doesnt seem to match PRM?" *-*
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#include "test.h"
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.include "testutils.inc"
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start
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//
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// Constants and Defines
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//
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include(gen_int.inc)
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include(selfcheck.inc)
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include(std.inc)
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include(mmrs.inc)
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include(symtable.inc)
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#ifndef STACKSIZE
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#define STACKSIZE 0x100 // change for how much stack you need
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#endif
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#ifndef ITABLE
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#define ITABLE 0xF0000000
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#endif
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GEN_INT_INIT(ITABLE) // set location for interrupt table
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//
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// Reset/Bootstrap Code
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// (Here we should set the processor operating modes, initialize registers,
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// etc.)
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//
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BOOT:
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INIT_R_REGS(0); // initialize general purpose regs
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INIT_P_REGS(0); // initialize the pointers
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INIT_I_REGS(0); // initialize the dsp address regs
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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CLI R1; // inhibit events during MMR writes
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LD32_LABEL(sp, USTACK); // setup the user stack pointer
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USP = SP;
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LD32_LABEL(sp, KSTACK); // setup the kernel stack pointer
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FP = SP; // and frame pointer
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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P0 += 4; // EVT0 not used (Emulation)
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P0 += 4; // EVT1 not used (Reset)
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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P0 += 4; // EVT4 not used (Global Interrupt Enable)
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R1 = -1; // Change this to mask interrupts (*)
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CSYNC; // wait for MMR writes to finish
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STI R1; // sync and reenable events (implicit write to IMASK)
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DUMMY:
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A0 = 0; // reset accumulators
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A1 = 0;
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R0 = 0 (Z);
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LT0 = r0; // set loop counters to something deterministic
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LB0 = r0;
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LC0 = r0;
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LT1 = r0;
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LB1 = r0;
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LC1 = r0;
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ASTAT = r0; // reset other internal regs
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SYSCFG = r0;
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RETS = r0; // prevent X's breaking LINK instruction
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// The following code sets up the test for running in USER mode
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LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
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// ReturnFromInterrupt (RTI)
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RETI = r0; // We need to load the return address
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// Comment the following line for a USER Mode test
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JUMP STARTSUP; // jump to code start for SUPERVISOR mode
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RTI;
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STARTSUP:
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LD32_LABEL(p1, BEGIN);
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LD32(p0, EVT15);
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CLI R1; // inhibit events during write to MMR
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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CSYNC; // wait for it
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STI R1; // reenable events with proper imask
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RAISE 15; // after we RTI, INT 15 should be taken
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RTI;
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//
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// The Main Program
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//
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STARTUSER:
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LINK 0; // change for how much stack frame space you need.
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JUMP BEGIN;
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//*********************************************************************
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BEGIN:
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// COMMENT the following line for USER MODE tests
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[ -- SP ] = RETI; // enable interrupts in supervisor mode
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// **** YOUR CODE GOES HERE ****
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// PUT YOUR TEST HERE!
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// Slot 0 can only be LDST LOAD with search instruction (2 instrs)
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.dw 0xcc0d //(R0,R1)=SEARCH R2(GT)||[P0]=R3||NOP;
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.dw 0x0210
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.dw 0x9303
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.dw 0x0000
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// (r0,r1) = search r2 gt, nop, r3 = [i0]; // nop supposedly ok
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( R0 , R1 ) = SEARCH R2 (GT) || R4 = [ P0 ++ P1 ] || NOP;
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// only nop or dspLDST allowed in slot 1 (1 instr)
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// a0 = r0, nop, [p0] = r3;
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.dw 0xCC09; // can't assemble
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.dw 0x2000;
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.dw 0x0000;
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.dw 0x9303;
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// Slot 0 illegal opcodes (1 instr)
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// a0 = r0, raise 15, nop;
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.dw 0xCC09; // can't assemble
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.dw 0x2000;
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.dw 0x009F;
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.dw 0x0000;
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// multiissue with two stores (8 instrs)
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.dw 0xcc09 //A0=R0||W[P3]=R5.L||[I0]=R4;
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.dw 0x2000
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.dw 0x8b5b
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[I2]=R2||[I0]=R4;
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.dw 0x2000
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.dw 0x9f12
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[P3]=R0||[I0]=R4;
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.dw 0x2000
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.dw 0x9318
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[P3]=P0||[I0]=R4;
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.dw 0x2000
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.dw 0x9358
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[FP+-36]=R0||[I0]=R4;
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.dw 0x2000
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.dw 0xbb70
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[FP+-48]=P0||[I0]=R4;
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.dw 0x2000
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.dw 0xbb48
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[P3+0x20]=R1||[I0]=R4;
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.dw 0x2000
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.dw 0xb219
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.dw 0x9f04
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.dw 0xcc09 //A0=R0||[P3+0x20]=P1||[I0]=R4;
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.dw 0x2000
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.dw 0xbe19
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.dw 0x9f04
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// multiissue two instructions can't modify same ireg (6 instrs)
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.dw 0xcc09 //A0=R0||I0+=M1(BREV)||R1.L=W[I0++];
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.dw 0x2000
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.dw 0x9ee4
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.dw 0x9c21
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.dw 0xcc09 //A0=R0||I1-=M3||R0=[I1++M3];
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.dw 0x2000
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.dw 0x9e7d
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.dw 0x9de8
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.dw 0xcc09 //A0=R0||I2+=2||W[I2++]=R0.L;
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.dw 0x2000
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.dw 0x9f62
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.dw 0x9e30
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.dw 0xcc09 //A0=R0||I3-=4||[I3++M1]=R7;
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.dw 0x2000
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.dw 0x9f6f
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.dw 0x9fbf
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.dw 0xcc09 //A0=R0||R1.L=W[I1++]||W[I1++]=R2.L;
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.dw 0x2000
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.dw 0x9c29
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.dw 0x9e2a
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.dw 0xcc09 //A0=R0||[I2++M3]=R7||R6=[I2++M0];
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.dw 0x2000
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.dw 0x9ff7
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.dw 0x9d96
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// multiissue two instructions can't load same dreg (9 instrs)
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.dw 0xcc09 //A0=R0||R0.L=W[P0++P2]||R0=[I0++];
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.dw 0x2000
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.dw 0x8210
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.dw 0x9c00
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.dw 0xcc09 //A0=R0||R1=W[P0++P3](X)||R1.L=W[I2];
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.dw 0x2000
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.dw 0x8e58
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.dw 0x9d31
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.dw 0xcc09 //A0=R0||R2=W[P0++P3](X)||R2=[I1++M3];
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.dw 0x2000
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.dw 0x8e98
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.dw 0x9dea
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.dw 0xcc09 //A0=R0||R3=[I0++]||R3=[I1++];
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.dw 0x2000
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.dw 0x9c03
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.dw 0x9c0b
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.dw 0xcc09 //A0=R0||R4.L=W[I2]||R4.L=W[I3];
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.dw 0x2000
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.dw 0x9d34
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.dw 0x9d3c
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.dw 0xcc09 //A0=R0||R5=[I1++M3]||R5.L=W[I2++];
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.dw 0x2000
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.dw 0x9ded
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.dw 0x9c35
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.dw 0xcc09 //A0=R0||R6=[P0]||R6=[I0++];
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.dw 0x2000
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.dw 0x9106
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.dw 0x9c06
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.dw 0xcc09 //A0=R0||R7=[FP+-56]||R7.L=W[I1];
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.dw 0x2000
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.dw 0xb927
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.dw 0x9d2f
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.dw 0xcc09 //A0=R0||R0=W[P1+0x1e](X)||R0=[I0++];
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.dw 0x2000
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.dw 0xabc8
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.dw 0x9c00
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// dsp32alu instructions with one dest and slot 0 multi with same dest (1 ins)
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.dw 0xcc00 //R0=R2+|+R3||R0=W[P1+0x1e](X)||NOP;
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.dw 0x0013
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.dw 0xabc8
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.dw 0x0000
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// other slot 0 dreg cases already covered
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// dsp32alu one dest and slot 1 multi with same dest (1 ins)
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.dw 0xcc18 //R1=BYTEPACK(R4,R5)||NOP||R1.L=W[I2];
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.dw 0x0225
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.dw 0x0000
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.dw 0x9d31
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// other slot 1 dreg dest cases already covered
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// dsp32alu dual dests and slot 0 multi with either same dest (2 instrs)
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.dw 0xcc18 //(R2,R3)=BYTEUNPACKR1:0||R2=W[P0++P3](X)||NOP;
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.dw 0x4680
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.dw 0x8e98
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.dw 0x0000
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.dw 0xcc01 //R2=R2+|+R3,R3=R2-|-R3||R3=[P3]||NOP;
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.dw 0x0693
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.dw 0x911b
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.dw 0x0000
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// dsp32alu dual dests and slot 1 multi with either same dest (2 instrs)
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.dw 0xcc18 //(R4,R5)=BYTEUNPACKR1:0||NOP||R4=[I1++M3];
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.dw 0x4b00
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.dw 0x0000
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.dw 0x9dec
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.dw 0xcc01 //R4=R2+|+R3,R5=R2-|-R3||NOP||R5.L=W[I2++];
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.dw 0x0b13
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.dw 0x0000
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.dw 0x9c35
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// dsp32shift one dest and slot 0 multi with same dest (1 instruction)
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.dw 0xce0d //R6=ALIGN8(R4,R5)||R6=[P0]||NOP;
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.dw 0x0c2c
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.dw 0x9106
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.dw 0x0000
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// dsp32shift one dest and slot 1 multi with same dest (1 instruction)
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.dw 0xce00 //R7.L=ASHIFTR0.HBYR7.L||NOP||R7.L=W[I1];
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.dw 0x1e38
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.dw 0x0000
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.dw 0x9d2f
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// dsp32shift two dests and slot 0 multi with either same dest (2 instrs)
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.dw 0xce08 //BITMUX(R0,R1,A0)(ASR)||R0.L=W[P0++P2]||NOP;
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.dw 0x0001
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.dw 0x8210
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.dw 0x0000
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.dw 0xce08 //BITMUX(R2,R3,A0)(ASL)||R3=[I0++]||NOP;
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.dw 0x4013
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.dw 0x9c03
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.dw 0x0000
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// dsp32shift two dests and slot 1 multi with either same dest (2 instrs)
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.dw 0xce08 //BITMUX(R4,R5,A0)(ASR)||NOP||R4.H=W[I3];
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.dw 0x0025
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.dw 0x0000
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.dw 0x9d5c
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.dw 0xce08 //BITMUX(R6,R7,A0)(ASL)||NOP||R7.L=W[I1];
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.dw 0x4037
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.dw 0x0000
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.dw 0x9d2f
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// dsp32shiftimm one dest and slot 0 with same dest (1 instr)
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.dw 0xce80 //R1.L=R0.H<<0x7||R1=W[P0++P3](X)||NOP;
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.dw 0x1238
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.dw 0x8e58
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.dw 0x0000
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// dsp32shiftimm one dest and slot 1 with same dest (1 instr)
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.dw 0xce81 //R5=R2<<0x9(V)||NOP||R5.L=W[I2++];
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.dw 0x0a4a
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.dw 0x0000
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.dw 0x9c35
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// dsp32mac one dest and slot 0 multi with same dest (1 inst)
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.dw 0xc805 //A0+=R1.H*R0.L,R6.H=(A1+=R1.L*R0.H)||R6=W[P0++P3](X)||NOP;
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.dw 0x4d88
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.dw 0x8f98
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.dw 0x0000
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// dsp32mult one dest and slot 0 multi with same dest (1 inst)
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.dw 0xca04 //R7.H=R3.L*R4.H||R7=[FP+-56]||NOP;
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.dw 0x41dc
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.dw 0xb927
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.dw 0x0000
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// dsp32 mac one dest and slot 1 multi with same dest (1 inst)
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.dw 0xc805 //A0+=R1.H*R0.L,R0.H=(A1+=R1.L*R0.H)||NOP||R0=[I0++];
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.dw 0x4c08
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.dw 0x0000
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.dw 0x9c00
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// dsp32mult one dest and slot 1 multi with same dest (1 inst)
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.dw 0xca04 //R1.H=R3.L*R4.H||NOP||R1.H=W[I1];
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.dw 0x405c
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.dw 0x0000
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.dw 0x9d49
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// dsp32mac write to register pair and slot 0 same dest - even (1 instr)
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.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||R2=W[P0++P3](X)||NOP;
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.dw 0x6c88
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.dw 0x8e98
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.dw 0x0000
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// dsp32mult write to register pair and slot 0 same dest - even (1 instr)
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.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R4=[P0++P1]||NOP;
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.dw 0x6508
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.dw 0x8108
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.dw 0x0000
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// dsp32mac write to register pair and slot 1 same dest - even (1 instr)
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.dw 0xc80d //R3=(A1+=R1.L*R0.H),R2=(A0+=R1.H*R0.L)||NOP||R2=[I1++M3];
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.dw 0x6c88
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.dw 0x0000
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.dw 0x9dea
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// dsp32mult write to register pair and slot 1 same dest - even (1 instr)
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.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R4=[I1++M3];
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.dw 0x6508
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.dw 0x0000
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.dw 0x9dec
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// dsp32mac write to register pair and slot 0 same dest - odd (1 instr)
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.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||R3=W[P0++P3](X)||NOP;
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.dw 0x4c88
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.dw 0x8ed8
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.dw 0x0000
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// dsp32mult write to register pair and slot 0 same dest - odd (1 instr)
|
|
|
|
|
|
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||R5=[P0++P1]||NOP;
|
|
.dw 0x6508
|
|
.dw 0x8148
|
|
.dw 0x0000
|
|
|
|
// dsp32mac write to register pair and slot 1 same dest - odd (1 instr)
|
|
|
|
|
|
.dw 0xc80d //A0+=R1.H*R0.L,R3=(A1+=R1.L*R0.H)||NOP||R3=[I1++M3];
|
|
.dw 0x4c88
|
|
.dw 0x0000
|
|
.dw 0x9deb
|
|
|
|
// dsp32mult write to register pair and slot 1 same dest - odd (1 instr)
|
|
|
|
|
|
.dw 0xca0c //R5=R1.L*R0.H,R4=R1.H*R0.L||NOP||R5=[I1++M3];
|
|
.dw 0x6508
|
|
.dw 0x0000
|
|
.dw 0x9ded
|
|
|
|
// CHECKER
|
|
|
|
CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
|
|
// Xhandler counts all EXCAUSE = 0x22;
|
|
CHECKREG(r5, 53); // count of all Illegal Combination Exceptions.
|
|
|
|
END:
|
|
dbg_pass; // End the test
|
|
|
|
//*********************************************************************
|
|
|
|
//
|
|
// Handlers for Events
|
|
//
|
|
|
|
NHANDLE: // NMI Handler 2
|
|
RTN;
|
|
|
|
XHANDLE: // Exception Handler 3
|
|
// 16 bit illegal opcode handler - skips bad instruction
|
|
|
|
[ -- SP ] = ASTAT; // save what we damage
|
|
[ -- SP ] = ( R7:6 );
|
|
R7 = SEQSTAT;
|
|
R7 <<= 26;
|
|
R7 >>= 26; // only want EXCAUSE
|
|
R6 = 0x22; // EXCAUSE 0x22 means I-Fetch Undefined Instruction
|
|
CC = r7 == r6;
|
|
IF CC JUMP ILLEGALCOMBINATION; // If EXCAUSE != 0x22 then leave
|
|
|
|
dbg_fail;
|
|
JUMP.S OUT; // if the EXCAUSE is wrong the test will infinite loop
|
|
|
|
ILLEGALCOMBINATION:
|
|
R7 = RETX; // Fix up return address
|
|
|
|
R7 += 8; // skip offending 64 bit instruction
|
|
|
|
RETX = r7; // and put back in RETX
|
|
|
|
R5 += 1; // Increment global counter
|
|
|
|
OUT:
|
|
( R7:6 ) = [ SP ++ ];
|
|
ASTAT = [sp++];
|
|
|
|
RTX;
|
|
|
|
HWHANDLE: // HW Error Handler 5
|
|
RTI;
|
|
|
|
THANDLE: // Timer Handler 6
|
|
RTI;
|
|
|
|
I7HANDLE: // IVG 7 Handler
|
|
RTI;
|
|
|
|
I8HANDLE: // IVG 8 Handler
|
|
RTI;
|
|
|
|
I9HANDLE: // IVG 9 Handler
|
|
RTI;
|
|
|
|
I10HANDLE: // IVG 10 Handler
|
|
RTI;
|
|
|
|
I11HANDLE: // IVG 11 Handler
|
|
RTI;
|
|
|
|
I12HANDLE: // IVG 12 Handler
|
|
RTI;
|
|
|
|
I13HANDLE: // IVG 13 Handler
|
|
RTI;
|
|
|
|
I14HANDLE: // IVG 14 Handler
|
|
RTI;
|
|
|
|
I15HANDLE: // IVG 15 Handler
|
|
RTI;
|
|
|
|
|
|
// padding for the icache
|
|
|
|
EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
|
|
|
|
//
|
|
// Data Segment
|
|
//
|
|
|
|
.data
|
|
DATA:
|
|
.space (0x10);
|
|
|
|
// Stack Segments (Both Kernel and User)
|
|
|
|
.space (STACKSIZE);
|
|
KSTACK:
|
|
|
|
.space (STACKSIZE);
|
|
USTACK:
|