mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
223 lines
5.4 KiB
ArmAsm
223 lines
5.4 KiB
ArmAsm
# mach: bfin
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.include "testutils.inc"
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start
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I0 = 0 (X);
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I1 = 0 (X);
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A0 = A1 = 0;
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init_r_regs 0;
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ASTAT = R0;
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// This section of code will test the SAA instructions and sum of accumulators;
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loadsym I0, tstvecI;
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R0 = [ I0 ++ ];
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R2 = [ I0 ++ ];
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// +++++++++++++++ TG11.001 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 15 15 15 15 //
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// r1 ==> 0 0 0 0 //
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// //
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// Output:r2 ==> 0 0 0 30 //
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// r3 ==> 0 0 0 30 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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SAA ( R1:0 , R3:2 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x001e );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x001e );
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DBGA ( R7.H , 0x0000 );
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A1 = A0 = 0;
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// +++++++++++++++ TG11.002 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 15 15 15 15 //
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// r1 ==> 0 0 0 0 //
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// //
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// Output:r2 ==> 0 0 0 30 //
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// r3 ==> 0 0 0 30 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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SAA ( R1:0 , R3:2 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x001e );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x001e );
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DBGA ( R7.H , 0x0000 );
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A1 = A0 = 0;
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// +++++++++++++++ TG11.003 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 240 240 240 240 //
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// r1 ==> 0 0 0 0 //
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// //
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// Output:r2 ==> 0 480 //
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// r3 ==> 0 480 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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R0 = [ I0 ++ ];
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R2 = [ I0 ++ ];
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SAA ( R3:2 , R1:0 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x01e0 );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x01e0 );
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DBGA ( R7.H , 0x0000 );
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A1 = A0 = 0;
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// +++++++++++++++ TG11.004 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 240 240 240 240 //
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// r1 ==> 0 0 0 0 //
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// //
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// Output:r2 ==> 0 480 //
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// r3 ==> 0 480 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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SAA ( R1:0 , R3:2 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x01e0 );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x01e0 );
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DBGA ( R7.H , 0x0000 );
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A1 = A0 = 0;
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// +++++++++++++++ TG11.005 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 0 0 0 0 //
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// r1 ==> 0 0 0 0 //
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// //
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// Output:r2 ==> 0 0 //
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// r3 ==> 0 0 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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R0 = [ I0 ++ ];
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R2 = [ I0 ++ ];
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SAA ( R1:0 , R3:2 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0x0000 );
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// +++++++++++++++ TG11.006 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 255 255 255 255 //
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// r1 ==> 255 255 255 255 //
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// //
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// Output:r2 ==> 0 0 //
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// r3 ==> 0 0 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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SAA ( R3:2 , R1:0 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0x0000 );
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DBGA ( R7.H , 0x0000 );
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A1 = A0 = 0;
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// +++++++++++++++ TG12.001 +++++++++++++ //
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// //
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// HH HL LH LL //
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// Input: r0 ==> 255 255 255 255 //
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// r1 ==> 255 255 255 255 //
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// //
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// Output:r2 ==> 0 0 //
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// r3 ==> 0 0 //
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// ++++++++++++++++++++++++++++++++++++++++++ //
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loadsym I0, tstvecK;
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B0 = I0;
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L0.L = 4;
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loadsym I1, tstvecJ;
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B1 = I1;
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L1.L = 4;
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P0 = 64 (X);
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R0 = [ I0 ++ ];
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R2 = [ I1 ++ ];
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LSETUP ( l$1 , l$1 ) LC0 = P0;
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l$1:
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SAA ( R1:0 , R3:2 ) || R0 = [ I0 ++ ] || R1 = [ I1 ++ ];
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R2 = A1.L + A1.H, R3 = A0.L + A0.H;
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R7 = R2 + R3 (NS);
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DBGA ( R7.L , 0xff00 );
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DBGA ( R7.H , 0x0000 );
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R5.L = 0xfffa;
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A1 = R5;
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R5.H = 0xfff0;
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A0 = R5;
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loadsym I0, tstvecI;
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R0 = [ I0 ++ ];
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R2 = [ I0 ++ ];
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SAA ( R1:0 , R3:2 );
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R6 = A1.L + A1.H, R7 = A0.L + A0.H;
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DBGA ( R6.L , 0x000e );
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DBGA ( R6.H , 0x0000 );
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DBGA ( R7.L , 0xfffe );
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DBGA ( R7.H , 0xffff );
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pass
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.data
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tstvecI:
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.dw 0x0000
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.dw 0x0000
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.dw 0x0f0f
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.dw 0x0f0f
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.dw 0x0000
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.dw 0x0000
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.dw 0xf0f0
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.dw 0xf0f0
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.data
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tstvecJ:
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.dw 0xffff
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.data
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tstvecK:
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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.dw 0x0000
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