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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
215 lines
4.1 KiB
ArmAsm
215 lines
4.1 KiB
ArmAsm
// Immediate SHIFT test program.
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// Test r4 = ASHIFT (r2 by 10);
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// Test r4 = LSHIFT (r2 by 10);
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// Test r4 = ROT (r2 by 10);
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# mach: bfin
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.include "testutils.inc"
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start
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init_r_regs 0;
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ASTAT = R0;
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// load r0=0x80000001
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// load r1=0x00000000
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// load r2=0x00000000
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// load r3=0x00000000
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// load r4=0x00000000
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// load r5=0x00000000
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loadsym P0, data0;
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R0 = [ P0 ++ ];
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R1 = [ P0 ++ ];
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R2 = [ P0 ++ ];
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R3 = [ P0 ++ ];
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R4 = [ P0 ++ ];
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R5 = [ P0 ++ ];
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// arithmetic
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// left by largest positive magnitude of 31 (0x1f)
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// 8000 0001 -> 8000 0000
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R7 = 0;
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ASTAT = R7;
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R6 = R0 << 31;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x8000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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// arithmetic
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// left by 1
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// 8000 0001 -> 0000 0002
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R6 = R0 << 1;
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DBGA ( R6.L , 0x0002 );
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DBGA ( R6.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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// arithmetic
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// right by 1
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// 8000 0001 -> c000 0000
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R7 = 0;
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ASTAT = R7;
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R6 = R0 >>> 1;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0xc000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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// arithmetic
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// right by largest negative magnitude of -31
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// 8000 0001 -> ffff ffff
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R6 = R0 >>> 31;
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DBGA ( R6.L , 0xffff );
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DBGA ( R6.H , 0xffff );
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// logic
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// left by largest positive magnitude of 31 (0x1f)
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// 8000 0001 -> 8000 0000
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R6 = R0 << 31;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x8000 );
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// logic
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// left by 1
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// 8000 0001 -> 0000 0002
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R6 = R0 << 1;
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DBGA ( R6.L , 0x0002 );
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DBGA ( R6.H , 0x0000 );
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// logic
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// right by 1
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// 8000 0001 -> 4000 0000
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R6 = R0 >> 1;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x4000 );
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// logic
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// right by largest negative magnitude of -31
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// 8000 0001 -> 0000 0001
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R6 = R0 >> 31;
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DBGA ( R6.L , 0x0001 );
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DBGA ( R6.H , 0x0000 );
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// rot
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// left by 1
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// 8000 0001 -> 0000 0002 cc=1
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R7 = 0;
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CC = R7;
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R6 = ROT R0 BY 1;
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DBGA ( R6.L , 0x0002 );
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DBGA ( R6.H , 0x0000 );
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R7 = CC;
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DBGA ( R7.L , 0x0001 );
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// rot
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// right by -1
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// 8000 0001 -> 4000 0000 cc=1
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R7 = 0;
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CC = R7;
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R6 = ROT R0 BY -1;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x4000 );
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R7 = CC;
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DBGA ( R7.L , 0x0001 );
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// rot
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// right by largest positive magnitude of 31
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// 8000 0001 -> a000 0000 cc=0
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R7 = 0;
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CC = R7;
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R6 = ROT R0 BY 31;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0xa000 );
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R7 = CC;
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DBGA ( R7.L , 0x0000 );
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// rot
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// right by largest positive magnitude of 31 with cc=1
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// 8000 0001 cc=1 -> a000 0000 cc=0
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R7 = 1;
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CC = R7;
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R6 = ROT R0 BY 31;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0xe000 );
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R7 = CC;
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DBGA ( R7.L , 0x0000 );
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// rot
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// right by largest negative magnitude of -31
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// 8000 0001 -> 0000 0005 cc=0
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R7 = 0;
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CC = R7;
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R6 = ROT R0 BY -31;
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DBGA ( R6.L , 0x0005 );
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DBGA ( R6.H , 0x0000 );
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R7 = CC;
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DBGA ( R7.L , 0x0000 );
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// rot
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// right by largest negative magnitude of -31 with cc=1
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// 8000 0001 cc=1 -> 0000 0007 cc=0
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R7 = 1;
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CC = R7;
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R6 = ROT R0 BY -31;
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DBGA ( R6.L , 0x0007 );
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DBGA ( R6.H , 0x0000 );
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R7 = CC;
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DBGA ( R7.L , 0x0000 );
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// rot
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// left by 7
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// 8000 0001 cc=1 -> 0000 00e0 cc=0
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R7 = 1;
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CC = R7;
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R6 = ROT R0 BY 7;
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DBGA ( R6.L , 0x00e0 );
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DBGA ( R6.H , 0x0000 );
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R7 = CC;
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DBGA ( R7.L , 0x0000 );
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// rot by zero
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// 8000 0001 -> 8000 000
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R7 = 1;
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CC = R7;
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R6 = ROT R0 BY 0;
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DBGA ( R6.L , 0x0001 );
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DBGA ( R6.H , 0x8000 );
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R7 = CC;
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DBGA ( R7.L , 0x0001 );
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// 0 by 1
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R7 = 0;
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R0 = 0;
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ASTAT = R7;
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R6 = R0 << 1;
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DBGA ( R6.L , 0x0000 );
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DBGA ( R6.H , 0x0000 );
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CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
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CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
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CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
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pass
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.data
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data0:
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.dw 0x0001
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.dw 0x8000
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.dd 0x0000
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.dd 0x0
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.dd 0x0
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.dd 0x0
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.dd 0x0
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.dd 0x0
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