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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
336 lines
5.5 KiB
ArmAsm
336 lines
5.5 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_regmv_imlb_dep_stall/c_regmv_imlb_dep_stall.dsp
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// Spec Reference: regmv imlb-depepency stall
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# mach: bfin
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.include "testutils.inc"
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start
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// R-reg to I,M-reg to R-reg: stall
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imm32 r0, 0x00001110;
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imm32 r1, 0x00213330;
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imm32 r2, 0x04015550;
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imm32 r3, 0x06607770;
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imm32 r4, 0x08010990;
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imm32 r5, 0x0a01b0b0;
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imm32 r6, 0x0c01dd00;
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imm32 r7, 0x0e01f0f0;
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I0 = R0;
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R7 = I0;
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I1 = R1;
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R0 = I1;
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I2 = R2;
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R1 = I2;
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I3 = R3;
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R2 = I3;
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M0 = R4;
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R3 = M0;
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M1 = R5;
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R4 = M1;
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M2 = R6;
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R5 = M2;
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M3 = R7;
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R6 = M3;
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CHECKREG r0, 0x00213330;
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CHECKREG r1, 0x04015550;
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CHECKREG r2, 0x06607770;
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CHECKREG r3, 0x08010990;
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CHECKREG r4, 0x0A01B0B0;
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CHECKREG r5, 0x0C01DD00;
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CHECKREG r6, 0x00001110;
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CHECKREG r7, 0x00001110;
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R0 = M3;
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R1 = M2;
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R2 = M1;
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R3 = M0;
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R4 = I3;
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R5 = I2;
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R6 = I1;
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R7 = I0;
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CHECKREG r0, 0x00001110;
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CHECKREG r1, 0x0C01DD00;
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CHECKREG r2, 0x0A01B0B0;
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CHECKREG r3, 0x08010990;
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CHECKREG r4, 0x06607770;
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CHECKREG r5, 0x04015550;
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CHECKREG r6, 0x00213330;
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CHECKREG r7, 0x00001110;
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// R-to-M,I and to P-reg: stall
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imm32 i0, 0x00001111;
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imm32 i1, 0x12213341;
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imm32 i2, 0x14415541;
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imm32 i3, 0x16617741;
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imm32 m0, 0x18819941;
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imm32 m1, 0x1aa1bb41;
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imm32 m2, 0x1cc1dd41;
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imm32 m3, 0x1ee1ff41;
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M0 = R0;
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R0 = M0;
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M1 = R1;
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P1 = M1;
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M2 = R2;
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P2 = M2;
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M3 = R3;
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P3 = M3;
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I0 = R4;
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P4 = I0;
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I1 = R5;
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P5 = I1;
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I2 = R6;
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SP = I2;
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I3 = R7;
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FP = I3;
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CHECKREG r0, 0x00001110;
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CHECKREG p1, 0x0C01DD00;
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CHECKREG p2, 0x0A01B0B0;
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CHECKREG p3, 0x08010990;
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CHECKREG p4, 0x06607770;
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CHECKREG p5, 0x04015550;
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CHECKREG sp, 0x00213330;
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CHECKREG fp, 0x00001110;
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R0 = M0;
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R1 = M1;
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R2 = M2;
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R3 = M3;
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R4 = I0;
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R5 = I1;
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R6 = I2;
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R7 = I3;
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CHECKREG r0, 0x00001110;
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CHECKREG r1, 0x0C01DD00;
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CHECKREG r2, 0x0A01B0B0;
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CHECKREG r3, 0x08010990;
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CHECKREG r4, 0x06607770;
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CHECKREG r5, 0x04015550;
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CHECKREG r6, 0x00213330;
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CHECKREG r7, 0x00001110;
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// R-reg to L,B-reg to R-reg: stall
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imm32 r0, 0x20001112;
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imm32 r1, 0x22213332;
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imm32 r2, 0x21215552;
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imm32 r3, 0x21627772;
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imm32 r4, 0x21812992;
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imm32 r5, 0x21a1b2b2;
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imm32 r6, 0x21c1d222;
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imm32 r7, 0x21e1ff22;
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L0 = R1;
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R0 = L0;
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L1 = R2;
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R1 = L1;
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L2 = R3;
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R2 = L2;
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L3 = R4;
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R3 = L3;
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B0 = R5;
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R4 = B0;
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B1 = R6;
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R5 = B1;
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B2 = R7;
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R6 = B2;
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B3 = R0;
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R7 = B3;
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CHECKREG r0, 0x22213332;
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CHECKREG r1, 0x21215552;
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CHECKREG r2, 0x21627772;
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CHECKREG r3, 0x21812992;
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CHECKREG r4, 0x21A1B2B2;
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CHECKREG r5, 0x21C1D222;
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CHECKREG r6, 0x21E1FF22;
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CHECKREG r7, 0x22213332;
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R0 = L3;
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R1 = L2;
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R2 = L1;
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R3 = L0;
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R4 = B3;
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R5 = B2;
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R6 = B1;
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R7 = B0;
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CHECKREG r0, 0x21812992;
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CHECKREG r1, 0x21627772;
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CHECKREG r2, 0x21215552;
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CHECKREG r3, 0x22213332;
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CHECKREG r4, 0x22213332;
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CHECKREG r5, 0x21E1FF22;
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CHECKREG r6, 0x21C1D222;
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CHECKREG r7, 0x21A1B2B2;
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// R-reg to L,B-reg to P-reg: stall
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imm32 r0, 0x50001115;
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imm32 r1, 0x51213335;
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imm32 r2, 0x51415555;
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imm32 r3, 0x51617775;
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imm32 r4, 0x51819995;
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imm32 r5, 0x51a1bbb5;
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imm32 r6, 0x51c1ddd5;
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imm32 r7, 0x51e1fff5;
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L0 = R1;
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R0 = L0;
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L1 = R2;
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SP = L1;
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L2 = R3;
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FP = L2;
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L3 = R4;
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P1 = L3;
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B0 = R5;
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P2 = B0;
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B1 = R6;
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P3 = B1;
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B2 = R7;
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P4 = B2;
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B3 = R0;
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P5 = B3;
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CHECKREG r0, 0x51213335;
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CHECKREG p1, 0x51819995;
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CHECKREG p2, 0x51A1BBB5;
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CHECKREG p3, 0x51C1DDD5;
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CHECKREG p4, 0x51E1FFF5;
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CHECKREG p5, 0x51213335;
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CHECKREG sp, 0x51415555;
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CHECKREG fp, 0x51617775;
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R0 = L3;
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R1 = L2;
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R2 = L1;
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R3 = L0;
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R4 = B3;
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R5 = B2;
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R6 = B1;
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R7 = B0;
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CHECKREG r0, 0x51819995;
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CHECKREG r1, 0x51617775;
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CHECKREG r2, 0x51415555;
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CHECKREG r3, 0x51213335;
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CHECKREG r4, 0x51213335;
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CHECKREG r5, 0x51E1FFF5;
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CHECKREG r6, 0x51C1DDD5;
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CHECKREG r7, 0x51A1BBB5;
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// R-reg to I,M-reg to L,B-reg: stall
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imm32 r0, 0x00001111;
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imm32 r1, 0x72213337;
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imm32 r2, 0x74415557;
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imm32 r3, 0x76617777;
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imm32 r4, 0x78819997;
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imm32 r5, 0x7aa1bbb7;
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imm32 r6, 0x7cc1ddd7;
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imm32 r7, 0x77e1fff7;
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I0 = R0;
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L0 = I0;
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I1 = R1;
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L1 = I1;
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I2 = R2;
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L2 = I2;
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I3 = R3;
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L3 = I3;
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M0 = R4;
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B0 = M0;
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M1 = R5;
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B1 = M1;
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M2 = R6;
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B2 = M2;
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M3 = R7;
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B3 = M3;
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R0 = L3;
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R1 = L2;
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R2 = L1;
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R3 = L0;
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R4 = B3;
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R5 = B2;
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R6 = B1;
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R7 = B0;
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CHECKREG r0, 0x76617777;
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CHECKREG r1, 0x74415557;
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CHECKREG r2, 0x72213337;
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CHECKREG r3, 0x00001111;
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CHECKREG r4, 0x77E1FFF7;
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CHECKREG r5, 0x7CC1DDD7;
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CHECKREG r6, 0x7AA1BBB7;
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CHECKREG r7, 0x78819997;
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R0 = M3;
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R1 = M2;
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R2 = M1;
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R3 = M0;
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R4 = I3;
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R5 = I2;
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R6 = I1;
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R7 = I0;
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CHECKREG r0, 0x77E1FFF7;
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CHECKREG r1, 0x7CC1DDD7;
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CHECKREG r2, 0x7AA1BBB7;
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CHECKREG r3, 0x78819997;
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CHECKREG r4, 0x76617777;
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CHECKREG r5, 0x74415557;
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CHECKREG r6, 0x72213337;
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CHECKREG r7, 0x00001111;
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// R-reg to L,B-reg to I,M reg: stall
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imm32 r0, 0x00001111;
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imm32 r1, 0x81213338;
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imm32 r2, 0x81415558;
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imm32 r3, 0x81617778;
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imm32 r4, 0x81819998;
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imm32 r5, 0x81a1bbb8;
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imm32 r6, 0x81c1ddd8;
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imm32 r7, 0x81e1fff8;
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L0 = R0;
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I0 = L0;
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L1 = R1;
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I1 = L1;
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L2 = R2;
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I2 = L2;
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L3 = R3;
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I3 = L3;
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B0 = R4;
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M0 = B0;
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B1 = R5;
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M1 = B1;
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B2 = R6;
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M2 = B2;
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B3 = R7;
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M3 = B3;
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R0 = M0;
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R1 = M1;
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R2 = M2;
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R3 = M3;
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R4 = I0;
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R5 = I1;
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R6 = I2;
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R7 = I3;
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CHECKREG r0, 0x81819998;
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CHECKREG r1, 0x81A1BBB8;
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CHECKREG r2, 0x81C1DDD8;
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CHECKREG r3, 0x81E1FFF8;
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CHECKREG r4, 0x00001111;
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CHECKREG r5, 0x81213338;
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CHECKREG r6, 0x81415558;
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CHECKREG r7, 0x81617778;
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R0 = L3;
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R1 = L2;
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R2 = L1;
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R3 = L0;
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R4 = B3;
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R5 = B2;
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R6 = B1;
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R7 = B0;
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CHECKREG r0, 0x81617778;
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CHECKREG r1, 0x81415558;
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CHECKREG r2, 0x81213338;
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CHECKREG r3, 0x00001111;
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CHECKREG r4, 0x81E1FFF8;
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CHECKREG r5, 0x81C1DDD8;
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CHECKREG r6, 0x81A1BBB8;
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CHECKREG r7, 0x81819998;
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pass
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