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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
246 lines
4.1 KiB
ArmAsm
246 lines
4.1 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_regmv_dr_dep_nostall/c_regmv_dr_dep_nostall.dsp
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// Spec Reference: regmv dr-dep no stall
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000001;
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imm32 r1, 0x00110001;
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imm32 r2, 0x00220002;
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imm32 r3, 0x00330003;
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imm32 r4, 0x00440004;
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imm32 r5, 0x00550005;
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imm32 r6, 0x00660006;
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imm32 r7, 0x00770007;
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// R-reg to R-reg: no stall
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R0 = R0;
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R1 = R0;
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R2 = R1;
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R3 = R2;
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R4 = R3;
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R5 = R4;
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R6 = R5;
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R7 = R6;
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R0 = R7;
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CHECKREG r0, 0x00000001;
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CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x00000001;
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CHECKREG r3, 0x00000001;
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CHECKREG r4, 0x00000001;
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CHECKREG r5, 0x00000001;
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CHECKREG r6, 0x00000001;
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CHECKREG r7, 0x00000001;
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//imm32 p0, 0x00001111;
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imm32 p1, 0x22223333;
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imm32 p2, 0x44445555;
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imm32 p3, 0x66667777;
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imm32 p4, 0x88889999;
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imm32 p5, 0xaaaabbbb;
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imm32 fp, 0xccccdddd;
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imm32 sp, 0xeeeeffff;
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// P-reg to R-reg to I,M reg: no stall
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R0 = P0;
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I0 = R0;
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R1 = P1;
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I1 = R1;
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R2 = P2;
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I2 = R2;
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R3 = P3;
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I3 = R3;
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R4 = P4;
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M0 = R4;
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R5 = P5;
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M1 = R5;
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R6 = FP;
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M2 = R6;
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R7 = SP;
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M3 = R7;
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CHECKREG r1, 0x22223333;
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CHECKREG r2, 0x44445555;
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CHECKREG r3, 0x66667777;
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CHECKREG r4, 0x88889999;
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CHECKREG r5, 0xAAAABBBB;
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CHECKREG r6, 0xCCCCDDDD;
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CHECKREG r7, 0xEEEEFFFF;
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R0 = M3;
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R1 = M2;
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R2 = M1;
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R3 = M0;
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R4 = I3;
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R5 = I2;
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R6 = I1;
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R7 = I0;
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CHECKREG r0, 0xEEEEFFFF;
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CHECKREG r1, 0xCCCCDDDD;
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CHECKREG r2, 0xAAAABBBB;
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CHECKREG r3, 0x88889999;
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CHECKREG r4, 0x66667777;
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CHECKREG r5, 0x44445555;
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CHECKREG r6, 0x22223333;
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imm32 i0, 0x00001111;
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imm32 i1, 0x22223333;
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imm32 i2, 0x44445555;
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imm32 i3, 0x66667777;
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imm32 m0, 0x88889999;
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imm32 m0, 0xaaaabbbb;
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imm32 m0, 0xccccdddd;
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imm32 m0, 0xeeeeffff;
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// I,M-reg to R-reg to P-reg: no stall
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R0 = I0;
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P1 = R0;
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R1 = I1;
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P1 = R1;
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R2 = I2;
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P2 = R2;
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R3 = I3;
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P3 = R3;
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R4 = M0;
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P4 = R4;
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R5 = M1;
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P5 = R5;
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R6 = M2;
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SP = R6;
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R7 = M3;
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FP = R7;
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CHECKREG p1, 0x22223333;
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CHECKREG p2, 0x44445555;
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CHECKREG p3, 0x66667777;
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CHECKREG p4, 0xEEEEFFFF;
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CHECKREG p5, 0xAAAABBBB;
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CHECKREG sp, 0xCCCCDDDD;
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CHECKREG fp, 0xEEEEFFFF;
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imm32 i0, 0x10001111;
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imm32 i1, 0x12221333;
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imm32 i2, 0x14441555;
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imm32 i3, 0x16661777;
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imm32 m0, 0x18881999;
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imm32 m1, 0x1aaa1bbb;
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imm32 m2, 0x1ccc1ddd;
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imm32 m3, 0x1eee1fff;
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// I,M-reg to R-reg to L,B reg: no stall
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R0 = I0;
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L0 = R0;
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R1 = I1;
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L1 = R1;
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R2 = I2;
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L2 = R2;
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R3 = I3;
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L3 = R3;
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R4 = M0;
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B0 = R4;
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R5 = M1;
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B1 = R5;
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R6 = M2;
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B2 = R6;
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R7 = M3;
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B3 = R7;
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CHECKREG r0, 0x10001111;
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CHECKREG r1, 0x12221333;
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CHECKREG r2, 0x14441555;
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CHECKREG r3, 0x16661777;
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CHECKREG r4, 0x18881999;
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CHECKREG r5, 0x1AAA1BBB;
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CHECKREG r6, 0x1CCC1DDD;
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CHECKREG r7, 0x1EEE1FFF;
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R0 = L3;
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R1 = L2;
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R2 = L1;
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R3 = L0;
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R4 = B3;
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R5 = B2;
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R6 = B1;
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R7 = B0;
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CHECKREG r0, 0x16661777;
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CHECKREG r1, 0x14441555;
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CHECKREG r2, 0x12221333;
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CHECKREG r3, 0x10001111;
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CHECKREG r4, 0x1EEE1FFF;
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CHECKREG r5, 0x1CCC1DDD;
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CHECKREG r6, 0x1AAA1BBB;
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CHECKREG r7, 0x18881999;
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imm32 l0, 0x20003111;
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imm32 l1, 0x22223333;
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imm32 l2, 0x24443555;
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imm32 l3, 0x26663777;
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imm32 b0, 0x28883999;
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imm32 b0, 0x2aaa3bbb;
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imm32 b0, 0x2ccc3ddd;
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imm32 b0, 0x2eee3fff;
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// L,B-reg to R-reg to I,M reg: no stall
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R0 = L0;
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I0 = R0;
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R1 = L1;
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I1 = R1;
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R2 = L2;
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I2 = R2;
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R3 = L3;
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I3 = R3;
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R4 = B0;
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M0 = R4;
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R5 = B1;
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M1 = R5;
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R6 = B2;
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M2 = R6;
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R7 = B3;
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M3 = R7;
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R0 = M3;
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R1 = M2;
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R2 = M1;
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R3 = M0;
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R4 = I3;
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R5 = I2;
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R6 = I1;
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R7 = I0;
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CHECKREG r0, 0x1EEE1FFF;
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CHECKREG r1, 0x1CCC1DDD;
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CHECKREG r2, 0x1AAA1BBB;
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CHECKREG r3, 0x2EEE3FFF;
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CHECKREG r4, 0x26663777;
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CHECKREG r5, 0x24443555;
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CHECKREG r6, 0x22223333;
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CHECKREG r7, 0x20003111;
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imm32 r0, 0x00000030;
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imm32 r1, 0x00000031;
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imm32 r2, 0x00000003;
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imm32 r3, 0x00330003;
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imm32 r4, 0x00440004;
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imm32 r5, 0x00550005;
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imm32 r6, 0x00660006;
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imm32 r7, 0x00770007;
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// R-reg to R-reg to sysreg to Reg: no stall
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R3 = R0;
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ASTAT = R3;
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R6 = ASTAT;
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R4 = R1;
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RETS = R4;
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R7 = RETS;
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CHECKREG r0, 0x00000030;
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CHECKREG r1, 0x00000031;
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CHECKREG r2, 0x00000003;
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CHECKREG r3, 0x00000030;
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CHECKREG r4, 0x00000031;
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CHECKREG r5, 0x00550005;
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CHECKREG r6, 0x00000030;
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CHECKREG r7, 0x00000031;
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pass
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