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Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
425 lines
10 KiB
ArmAsm
425 lines
10 KiB
ArmAsm
//Original:/testcases/core/c_dsp32shift_ahalf_rn_s/c_dsp32shift_ahalf_rn_s.dsp
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// Spec Reference: dsp32shift ashift s
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# mach: bfin
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.include "testutils.inc"
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start
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// Ashift : positive data, count (+)=left (half reg)
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// d_lo = ashft (d_lo BY d_lo)
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// RLx by RLx
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imm32 r0, 0x00000000;
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R0.L = -1;
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imm32 r1, 0x00008001;
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imm32 r2, 0x00008002;
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imm32 r3, 0x00008003;
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imm32 r4, 0x00008004;
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imm32 r5, 0x00008005;
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imm32 r6, 0x00008006;
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imm32 r7, 0x00008007;
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//rl0 = ashift (rl0 by rl0);
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R1.L = ASHIFT R1.L BY R0.L (S);
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R2.L = ASHIFT R2.L BY R0.L (S);
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R3.L = ASHIFT R3.L BY R0.L (S);
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R4.L = ASHIFT R4.L BY R0.L (S);
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R5.L = ASHIFT R5.L BY R0.L (S);
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R6.L = ASHIFT R6.L BY R0.L (S);
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R7.L = ASHIFT R7.L BY R0.L (S);
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//CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x0000c000;
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CHECKREG r2, 0x0000c001;
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CHECKREG r3, 0x0000c001;
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CHECKREG r4, 0x0000c002;
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CHECKREG r5, 0x0000c002;
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CHECKREG r6, 0x0000c003;
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CHECKREG r7, 0x0000c003;
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imm32 r0, 0x00008001;
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R1.L = -1;
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imm32 r2, 0x00008002;
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imm32 r3, 0x00008003;
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imm32 r4, 0x00008004;
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imm32 r5, 0x00008005;
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imm32 r6, 0x00008006;
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imm32 r7, 0x00008007;
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R0.L = ASHIFT R0.L BY R1.L (S);
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//rl1 = ashift (rl1 by rl1);
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R2.L = ASHIFT R2.L BY R1.L (S);
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R3.L = ASHIFT R3.L BY R1.L (S);
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R4.L = ASHIFT R4.L BY R1.L (S);
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R5.L = ASHIFT R5.L BY R1.L (S);
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R6.L = ASHIFT R6.L BY R1.L (S);
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R7.L = ASHIFT R7.L BY R1.L (S);
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CHECKREG r0, 0x0000c000;
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//CHECKREG r1, 0x00000001;
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CHECKREG r2, 0x0000c001;
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CHECKREG r3, 0x0000c001;
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CHECKREG r4, 0x0000c002;
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CHECKREG r5, 0x0000c002;
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CHECKREG r6, 0x0000c003;
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CHECKREG r7, 0x0000c003;
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imm32 r0, 0x00008001;
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imm32 r1, 0x00008001;
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R2.L = -15;
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imm32 r3, 0x00008003;
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imm32 r4, 0x00008004;
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imm32 r5, 0x00008005;
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imm32 r6, 0x00008006;
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imm32 r7, 0x00008007;
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R0.L = ASHIFT R0.L BY R2.L (S);
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R1.L = ASHIFT R1.L BY R2.L (S);
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//rl2 = ashift (rl2 by rl2);
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R3.L = ASHIFT R3.L BY R2.L (S);
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R4.L = ASHIFT R4.L BY R2.L (S);
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R5.L = ASHIFT R5.L BY R2.L (S);
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R6.L = ASHIFT R6.L BY R2.L (S);
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R7.L = ASHIFT R7.L BY R2.L (S);
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x0000ffff;
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//CHECKREG r2, 0x0000000f;
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CHECKREG r3, 0x0000ffff;
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CHECKREG r4, 0x0000ffff;
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CHECKREG r5, 0x0000ffff;
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CHECKREG r6, 0x0000ffff;
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CHECKREG r7, 0x0000ffff;
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imm32 r0, 0x00008001;
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imm32 r1, 0x00008001;
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imm32 r2, 0x00008002;
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R3.L = -16;
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imm32 r4, 0x00008004;
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imm32 r5, 0x00008005;
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imm32 r6, 0x00008006;
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imm32 r7, 0x00008007;
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R0.L = ASHIFT R0.L BY R3.L (S);
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R1.L = ASHIFT R1.L BY R3.L (S);
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R2.L = ASHIFT R2.L BY R3.L (S);
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//rl3 = ashift (rl3 by rl3);
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R4.L = ASHIFT R4.L BY R3.L (S);
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R5.L = ASHIFT R5.L BY R3.L (S);
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R6.L = ASHIFT R6.L BY R3.L (S);
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R7.L = ASHIFT R7.L BY R3.L (S);
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CHECKREG r0, 0x0000ffff;
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CHECKREG r1, 0x0000ffff;
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CHECKREG r2, 0x0000ffff;
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//CHECKREG r3, 0x00000010;
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CHECKREG r4, 0x0000ffff;
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CHECKREG r5, 0x0000ffff;
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CHECKREG r6, 0x0000ffff;
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CHECKREG r7, 0x0000ffff;
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// d_lo = ashft (d_hi BY d_lo)
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// RHx by RLx
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imm32 r0, 0x00000000;
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imm32 r1, 0x80010000;
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imm32 r2, 0x80020000;
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imm32 r3, 0x80030000;
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imm32 r4, 0x80040000;
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imm32 r5, 0x80050000;
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imm32 r6, 0x80060000;
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imm32 r7, 0x80070000;
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R0.L = ASHIFT R0.H BY R0.L (S);
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R1.L = ASHIFT R1.H BY R0.L (S);
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R2.L = ASHIFT R2.H BY R0.L (S);
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R3.L = ASHIFT R3.H BY R0.L (S);
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R4.L = ASHIFT R4.H BY R0.L (S);
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R5.L = ASHIFT R5.H BY R0.L (S);
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R6.L = ASHIFT R6.H BY R0.L (S);
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R7.L = ASHIFT R7.H BY R0.L (S);
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x80018001;
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CHECKREG r2, 0x80028002;
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CHECKREG r3, 0x80038003;
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CHECKREG r4, 0x80048004;
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CHECKREG r5, 0x80058005;
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CHECKREG r6, 0x80068006;
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CHECKREG r7, 0x80078007;
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imm32 r0, 0x80010000;
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R1.L = -1;
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imm32 r2, 0x80020000;
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imm32 r3, 0x80030000;
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imm32 r4, 0x80040000;
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imm32 r5, 0x80050000;
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imm32 r6, 0x80060000;
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imm32 r7, 0x80070000;
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R0.L = ASHIFT R0.H BY R1.L (S);
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//rl1 = ashift (rh1 by rl1);
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R2.L = ASHIFT R2.H BY R1.L (S);
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R3.L = ASHIFT R3.H BY R1.L (S);
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R4.L = ASHIFT R4.H BY R1.L (S);
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R5.L = ASHIFT R5.H BY R1.L (S);
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R6.L = ASHIFT R6.H BY R1.L (S);
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R7.L = ASHIFT R7.H BY R1.L (S);
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CHECKREG r0, 0x8001c000;
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//CHECKREG r1, 0x00010001;
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CHECKREG r2, 0x8002c001;
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CHECKREG r3, 0x8003c001;
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CHECKREG r4, 0x8004c002;
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CHECKREG r5, 0x8005c002;
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CHECKREG r6, 0x8006c003;
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CHECKREG r7, 0x8007c003;
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imm32 r0, 0xa0010000;
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imm32 r1, 0xa0010000;
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R2.L = -15;
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imm32 r3, 0xa0030000;
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imm32 r4, 0xa0040000;
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imm32 r5, 0xa0050000;
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imm32 r6, 0xa0060000;
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imm32 r7, 0xa0070000;
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R0.L = ASHIFT R0.H BY R2.L (S);
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R1.L = ASHIFT R1.H BY R2.L (S);
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//rl2 = ashift (rh2 by rl2);
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R3.L = ASHIFT R3.H BY R2.L (S);
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R4.L = ASHIFT R4.H BY R2.L (S);
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R5.L = ASHIFT R5.H BY R2.L (S);
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R6.L = ASHIFT R6.H BY R2.L (S);
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R7.L = ASHIFT R7.H BY R2.L (S);
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CHECKREG r0, 0xa001ffff;
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CHECKREG r1, 0xa001ffff;
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//CHECKREG r2, 0x2002000f;
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CHECKREG r3, 0xa003ffff;
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CHECKREG r4, 0xa004ffff;
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CHECKREG r5, 0xa005ffff;
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CHECKREG r6, 0xa006ffff;
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CHECKREG r7, 0xa007ffff;
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imm32 r0, 0xb0010001;
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imm32 r1, 0xb0010001;
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imm32 r2, 0xb0020002;
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R3.L = -16;
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imm32 r4, 0xb0040004;
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imm32 r5, 0xb0050005;
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imm32 r6, 0xb0060006;
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imm32 r7, 0xb0070007;
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R0.L = ASHIFT R0.H BY R3.L (S);
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R1.L = ASHIFT R1.H BY R3.L (S);
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R2.L = ASHIFT R2.H BY R3.L (S);
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//rl3 = ashift (rh3 by rl3);
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R4.L = ASHIFT R4.H BY R3.L (S);
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R5.L = ASHIFT R5.H BY R3.L (S);
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R6.L = ASHIFT R6.H BY R3.L (S);
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R7.L = ASHIFT R7.H BY R3.L (S);
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CHECKREG r0, 0xb001ffff;
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CHECKREG r1, 0xb001ffff;
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CHECKREG r2, 0xb002ffff;
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//CHECKREG r3, 0x30030010;
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CHECKREG r4, 0xb004ffff;
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CHECKREG r5, 0xb005ffff;
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CHECKREG r6, 0xb006ffff;
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CHECKREG r7, 0xb007ffff;
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// d_hi = ashft (d_lo BY d_lo)
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// RLx by RLx
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imm32 r0, 0x00000001;
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imm32 r1, 0x00000001;
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imm32 r2, 0x00000002;
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imm32 r3, 0x00000003;
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imm32 r4, 0x00000000;
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imm32 r5, 0x00000005;
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imm32 r6, 0x00000006;
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imm32 r7, 0x00000007;
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R0.H = ASHIFT R0.L BY R4.L (S);
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R1.H = ASHIFT R1.L BY R4.L (S);
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R2.H = ASHIFT R2.L BY R4.L (S);
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R3.H = ASHIFT R3.L BY R4.L (S);
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//rh4 = ashift (rl4 by rl4);
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R5.H = ASHIFT R5.L BY R4.L (S);
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R6.H = ASHIFT R6.L BY R4.L (S);
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R7.H = ASHIFT R7.L BY R4.L (S);
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CHECKREG r0, 0x00010001;
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CHECKREG r1, 0x00010001;
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CHECKREG r2, 0x00020002;
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CHECKREG r3, 0x00030003;
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//CHECKREG r4, 0x00040004;
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CHECKREG r5, 0x00050005;
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CHECKREG r6, 0x00060006;
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CHECKREG r7, 0x00070007;
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imm32 r0, 0x00008001;
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imm32 r1, 0x00008001;
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imm32 r2, 0x00008002;
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imm32 r3, 0x00008003;
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imm32 r4, 0x00008004;
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R5.L = -1;
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imm32 r6, 0x00008006;
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imm32 r7, 0x00008007;
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R0.H = ASHIFT R0.L BY R5.L (S);
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R1.H = ASHIFT R1.L BY R5.L (S);
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R2.H = ASHIFT R2.L BY R5.L (S);
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R3.H = ASHIFT R3.L BY R5.L (S);
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R4.H = ASHIFT R4.L BY R5.L (S);
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//rh5 = ashift (rl5 by rl5);
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R6.H = ASHIFT R6.L BY R5.L (S);
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R7.H = ASHIFT R7.L BY R5.L (S);
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CHECKREG r0, 0xc0008001;
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CHECKREG r1, 0xc0008001;
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CHECKREG r2, 0xc0018002;
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CHECKREG r3, 0xc0018003;
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CHECKREG r4, 0xc0028004;
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//CHECKREG r5, 0x00020005;
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CHECKREG r6, 0xc0038006;
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CHECKREG r7, 0xc0038007;
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imm32 r0, 0x00009001;
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imm32 r1, 0x00009001;
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imm32 r2, 0x00009002;
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imm32 r3, 0x00009003;
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imm32 r4, 0x00009004;
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imm32 r5, 0x00009005;
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R6.L = -15;
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imm32 r7, 0x00009007;
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R0.H = ASHIFT R0.L BY R6.L (S);
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R1.H = ASHIFT R1.L BY R6.L (S);
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R2.H = ASHIFT R2.L BY R6.L (S);
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R3.H = ASHIFT R3.L BY R6.L (S);
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R4.H = ASHIFT R4.L BY R6.L (S);
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R5.H = ASHIFT R5.L BY R6.L (S);
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//rh6 = ashift (rl6 by rl6);
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R7.H = ASHIFT R7.L BY R6.L;
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CHECKREG r0, 0xffff9001;
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CHECKREG r1, 0xffff9001;
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CHECKREG r2, 0xffff9002;
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CHECKREG r3, 0xffff9003;
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CHECKREG r4, 0xffff9004;
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CHECKREG r5, 0xffff9005;
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//CHECKREG r6, 0x00006006;
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CHECKREG r7, 0xffff9007;
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imm32 r0, 0x0000a001;
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imm32 r1, 0x0000a001;
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imm32 r2, 0x0000a002;
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imm32 r3, 0x0000a003;
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imm32 r4, 0x0000a004;
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imm32 r5, 0x0000a005;
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imm32 r6, 0x0000a006;
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R7.L = -16;
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R0.H = ASHIFT R0.L BY R7.L (S);
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R1.H = ASHIFT R1.L BY R7.L (S);
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R2.H = ASHIFT R2.L BY R7.L (S);
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R3.H = ASHIFT R3.L BY R7.L (S);
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R4.H = ASHIFT R4.L BY R7.L (S);
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R5.H = ASHIFT R5.L BY R7.L (S);
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R6.H = ASHIFT R6.L BY R7.L (S);
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R7.H = ASHIFT R7.L BY R7.L (S);
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CHECKREG r0, 0xffffa001;
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CHECKREG r1, 0xffffa001;
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CHECKREG r2, 0xffffa002;
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CHECKREG r3, 0xffffa003;
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CHECKREG r4, 0xffffa004;
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CHECKREG r5, 0xffffa005;
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CHECKREG r6, 0xffffa006;
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//CHECKREG r7, 0x00007007;
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// d_lo = ashft (d_hi BY d_lo)
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// RHx by RLx
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imm32 r0, 0x80010000;
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imm32 r1, 0x80010000;
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imm32 r2, 0x80020000;
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imm32 r3, 0x80030000;
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R4.L = -1;
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imm32 r5, 0x80050000;
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imm32 r6, 0x80060000;
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imm32 r7, 0x80070000;
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R0.H = ASHIFT R0.H BY R4.L (S);
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R1.H = ASHIFT R1.H BY R4.L (S);
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R2.H = ASHIFT R2.H BY R4.L (S);
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R3.H = ASHIFT R3.H BY R4.L (S);
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//rh4 = ashift (rh4 by rl4);
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R5.H = ASHIFT R5.H BY R4.L (S);
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R6.H = ASHIFT R6.H BY R4.L (S);
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R7.H = ASHIFT R7.H BY R4.L (S);
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CHECKREG r0, 0xc0000000;
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CHECKREG r1, 0xc0000000;
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CHECKREG r2, 0xc0010000;
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CHECKREG r3, 0xc0010000;
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//CHECKREG r4, 0x00020000;
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CHECKREG r5, 0xc0020000;
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CHECKREG r6, 0xc0030000;
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CHECKREG r7, 0xc0030000;
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imm32 r0, 0x80010000;
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imm32 r1, 0x80010000;
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imm32 r2, 0x80020000;
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imm32 r3, 0x80030000;
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imm32 r4, 0x80040000;
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R5.L = -1;
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imm32 r6, 0x80060000;
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imm32 r7, 0x80070000;
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R0.H = ASHIFT R0.H BY R5.L (S);
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R1.H = ASHIFT R1.H BY R5.L (S);
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R2.H = ASHIFT R2.H BY R5.L (S);
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R3.H = ASHIFT R3.H BY R5.L (S);
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R4.H = ASHIFT R4.H BY R5.L (S);
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//rh5 = ashift (rh5 by rl5);
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R6.H = ASHIFT R6.H BY R5.L (S);
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R7.H = ASHIFT R7.H BY R5.L (S);
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CHECKREG r0, 0xc0000000;
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CHECKREG r1, 0xc0000000;
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CHECKREG r2, 0xc0010000;
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CHECKREG r3, 0xc0010000;
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CHECKREG r4, 0xc0020000;
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//CHECKREG r5, 0x28020000;
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CHECKREG r6, 0xc0030000;
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CHECKREG r7, 0xc0030000;
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imm32 r0, 0xd0010000;
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imm32 r1, 0xd0010000;
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imm32 r2, 0xd0020000;
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imm32 r3, 0xd0030000;
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imm32 r4, 0xd0040000;
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imm32 r5, 0xd0050000;
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R6.L = -15;
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imm32 r7, 0xd0070000;
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R0.L = ASHIFT R0.H BY R6.L (S);
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R1.L = ASHIFT R1.H BY R6.L (S);
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R2.L = ASHIFT R2.H BY R6.L (S);
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R3.L = ASHIFT R3.H BY R6.L (S);
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R4.L = ASHIFT R4.H BY R6.L (S);
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R5.L = ASHIFT R5.H BY R6.L (S);
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//rl6 = ashift (rh6 by rl6);
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R7.L = ASHIFT R7.H BY R6.L;
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CHECKREG r0, 0xd001ffff;
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CHECKREG r1, 0xd001ffff;
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CHECKREG r2, 0xd002ffff;
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CHECKREG r3, 0xd003ffff;
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CHECKREG r4, 0xd004ffff;
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CHECKREG r5, 0xd005ffff;
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//CHECKREG r6, 0x60060000;
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CHECKREG r7, 0xd007ffff;
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imm32 r0, 0xe0010000;
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imm32 r1, 0xe0010000;
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imm32 r2, 0xe0020000;
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imm32 r3, 0xe0030000;
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imm32 r4, 0xe0040000;
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imm32 r5, 0xe0050000;
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imm32 r6, 0xe0060000;
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R7.L = -16;
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R0.H = ASHIFT R0.H BY R7.L (S);
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R1.H = ASHIFT R1.H BY R7.L (S);
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R2.H = ASHIFT R2.H BY R7.L (S);
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R3.H = ASHIFT R3.H BY R7.L (S);
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R4.H = ASHIFT R4.H BY R7.L (S);
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R5.H = ASHIFT R5.H BY R7.L (S);
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R6.H = ASHIFT R6.H BY R7.L (S);
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//rh7 = ashift (rh7 by rl7);
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CHECKREG r0, 0xffff0000;
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CHECKREG r1, 0xffff0000;
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CHECKREG r2, 0xffff0000;
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CHECKREG r3, 0xffff0000;
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CHECKREG r4, 0xffff0000;
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CHECKREG r5, 0xffff0000;
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CHECKREG r6, 0xffff0000;
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//CHECKREG r7, -16;
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pass
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