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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
225 lines
3.7 KiB
ArmAsm
225 lines
3.7 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_ccflag_dr_imm3/c_ccflag_dr_imm3.dsp
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// Spec Reference: ccflag dr-imm3
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0x00000001;
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imm32 r1, 0x00000002;
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imm32 r2, 0x00000003;
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imm32 r3, 0x00000004;
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imm32 r4, 0x00770088;
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imm32 r5, 0x009900aa;
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imm32 r6, 0x00bb00cc;
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imm32 r7, 0x00000000;
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ASTAT = R7;
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R4 = ASTAT;
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// positive dreg EQUAL to positive imm3
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CC = R0 == 1;
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R5 = ASTAT;
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CC = R0 < 1;
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R6 = ASTAT;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00001025;
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CHECKREG r6, 0x00001005;
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CC = R0 <= 1;
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R5 = ASTAT;
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CC = R0 < 1;
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R6 = ASTAT;
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CC = R0 <= 1;
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R7 = ASTAT;
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CHECKREG r5, 0x00001025;
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CHECKREG r6, 0x00001005;
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CHECKREG r7, 0x00001025;
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// positive dreg GREATER than to positive imm3
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CC = R1 == 1;
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R5 = ASTAT;
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CC = R1 < 1;
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R6 = ASTAT;
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CC = R1 <= 1;
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R7 = ASTAT;
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CHECKREG r5, 0x00001004; // carry
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CHECKREG r6, 0x00001004;
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CHECKREG r7, 0x00001004;
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// positive dreg LESS than to positive imm3
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CC = R0 == 2;
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R5 = ASTAT;
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CC = R0 < 2;
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R6 = ASTAT;
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CC = R0 <= 2;
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R7 = ASTAT;
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CHECKREG r5, 0x00000002;
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CHECKREG r6, 0x00000022;
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CHECKREG r7, 0x00000022;
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// positive dreg GREATER than to neg imm3
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CC = R2 == -4;
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R5 = ASTAT;
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CC = R2 < -4;
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R6 = ASTAT;
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CC = R2 <= -4;
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R7 = ASTAT;
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CHECKREG r5, 0x00000000;
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CHECKREG r6, 0x00000000;
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CHECKREG r7, 0x00000000;
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imm32 r0, -1;
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imm32 r1, -2;
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imm32 r2, -3;
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imm32 r3, -4;
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// negative dreg and positive imm3
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R7 = 0;
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ASTAT = R7;
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R4 = ASTAT;
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CC = R3 == 1;
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R5 = ASTAT;
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CC = R3 < 1;
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R6 = ASTAT;
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CC = R3 <= 1;
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R7 = ASTAT;
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CHECKREG r4, 0x00000000;
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CHECKREG r5, 0x00001006;
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CHECKREG r6, 0x00001026;
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CHECKREG r7, 0x00001026;
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// negative dreg LESS than neg imm3
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CC = R2 == -1;
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R4 = ASTAT;
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CC = R2 < -1;
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R5 = ASTAT;
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CC = R2 <= -1;
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R6 = ASTAT;
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CHECKREG r4, 0x00000002;
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CHECKREG r5, 0x00000022;
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CHECKREG r6, 0x00000022;
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// negative dreg GREATER neg imm3
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CC = R0 == -4;
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R4 = ASTAT;
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CC = R0 < -4;
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R5 = ASTAT;
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CC = R0 <= -4;
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R6 = ASTAT;
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CHECKREG r4, 0x00001004;
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CHECKREG r5, 0x00001004;
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CHECKREG r6, 0x00001004;
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imm32 r0, 0x00000000;
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imm32 r1, 0x00000000;
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imm32 r2, 0x00000000;
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imm32 r3, 0x00000000;
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imm32 r4, 0x00000001;
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imm32 r5, 0x00000002;
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imm32 r6, 0x00000003;
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imm32 r7, 0x00000004;
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ASTAT = R0;
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R3 = ASTAT;
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// positive dreg EQUAL to positive imm3
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CC = R4 == 1;
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R1 = ASTAT;
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CC = R4 < 1;
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R2 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00001025;
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CHECKREG r2, 0x00001005;
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CC = R4 <= 1;
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R1 = ASTAT;
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CC = R4 < 1;
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R2 = ASTAT;
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CC = R4 <= 1;
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R3 = ASTAT;
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CHECKREG r1, 0x00001025;
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CHECKREG r2, 0x00001005;
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CHECKREG r3, 0x00001025;
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// positive dreg GREATER than to positive imm3
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CC = R5 == 1;
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R1 = ASTAT;
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CC = R5 < 1;
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R2 = ASTAT;
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CC = R5 <= 1;
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R3 = ASTAT;
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CHECKREG r1, 0x00001004; // carry
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CHECKREG r2, 0x00001004;
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CHECKREG r3, 0x00001004;
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// positive dreg LESS than to positive imm3
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CC = R6 == 2;
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R1 = ASTAT;
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CC = R6 < 2;
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R2 = ASTAT;
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CC = R6 <= 2;
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R3 = ASTAT;
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CHECKREG r1, 0x00001004;
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CHECKREG r2, 0x00001004;
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CHECKREG r3, 0x00001004;
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// positive dreg GREATER than to neg imm3
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CC = R6 == -4;
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R1 = ASTAT;
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CC = R6 < -4;
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R2 = ASTAT;
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CC = R6 <= -4;
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R3 = ASTAT;
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CHECKREG r1, 0x00000000;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0x00000000;
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imm32 r4, -1;
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imm32 r5, -2;
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imm32 r6, -3;
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imm32 r7, -4;
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// negative dreg and positive imm3
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R3 = 0;
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ASTAT = R3;
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R0 = ASTAT;
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CC = R7 == 1;
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R1 = ASTAT;
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CC = R7 < 1;
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R2 = ASTAT;
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CC = R7 <= 1;
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R3 = ASTAT;
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CHECKREG r0, 0x00000000;
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CHECKREG r1, 0x00001006;
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CHECKREG r2, 0x00001026;
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CHECKREG r3, 0x00001026;
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// negative dreg LESS than neg imm3
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CC = R6 == -1;
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R0 = ASTAT;
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CC = R6 < -1;
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R1 = ASTAT;
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CC = R6 <= -1;
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R2 = ASTAT;
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CHECKREG r0, 0x00000002;
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CHECKREG r1, 0x00000022;
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CHECKREG r2, 0x00000022;
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// negative dreg GREATER neg imm3
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CC = R4 == -4;
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R0 = ASTAT;
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CC = R4 < -4;
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R1 = ASTAT;
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CC = R4 <= -4;
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R2 = ASTAT;
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CHECKREG r0, 0x00001004;
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CHECKREG r1, 0x00001004;
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CHECKREG r2, 0x00001004;
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pass;
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