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fd195909ce
This patch adds new variant (nXS) of DSB memory barrier instruction available in Armv8.7-a. New nXS variant has different encoding in comparison with pre Armv8.7-a DSB memory barrier variant thus new instruction and new operand was added. DSB memory nXS barrier variant specifies the limitation on the barrier operation. Allowed values are: DSB SYnXS|#28 DSB ISHnXS|#24 DSB NSHnXS|#20 DSB OSHnXS|#16 Please note that till now, for barriers, barrier operation was encoded in 4-bit unsigned immediate CRm field (in the range 0 to 15). For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned assembly instruction immediate, encoded in instruction in two bits CRm<3:2>: CRm<3:2> #imm 00 16 01 20 10 24 11 28 This patch extends current AArch64 barrier instructions with above mapping. Notable patch changes include: + New DSB memory barrier variant encoding for Armv8.7-a. + New operand BARRIER_DSB_NXS for above instruction in order to distinguish between existing and new DSB instruction flavour. + New set of DSB nXS barrier options. + New instruction inserter and extractor map between instruction immediate 5-bit value and 2-bit CRm field of the instruction itself (see FLD_CRm_dsb_nxs). + Regeneration of aarch64-[asm|dis|opc]-2.c files. + Test cases to cover new instruction assembling and disassembling. For more details regarding DSB memory barrier instruction and its Armv8.7-a flavour please refer to Arm A64 Instruction set documentation for Armv8-A architecture profile, see document pages 132-133 of [0]. [0]: https://developer.arm.com/docs/ddi0596/i gas/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * NEWS: Docs update. * config/tc-aarch64.c (parse_operands): Add AARCH64_OPND_BARRIER_DSB_NXS handler. (md_begin): Add content of aarch64_barrier_dsb_nxs_options to aarch64_barrier_opt_hsh hash. * testsuite/gas/aarch64/system-4-invalid.d: New test. * testsuite/gas/aarch64/system-4-invalid.l: New test. * testsuite/gas/aarch64/system-4-invalid.s: New test. * testsuite/gas/aarch64/system-4.d: New test. * testsuite/gas/aarch64/system-4.s: New test. include/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * opcode/aarch64.h (enum aarch64_opnd): New operand AARCH64_OPND_BARRIER_DSB_NXS. (aarch64_barrier_dsb_nxs_options): Declare DSB nXS options. opcodes/ChangeLog: 2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter. * aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter ins_barrier_dsb_nx. * aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor. * aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor ext_barrier_dsb_nx. * aarch64-opc.c (aarch64_print_operand): New options table aarch64_barrier_dsb_nxs_options. * aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs. * aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier Armv8.7-a instruction. * aarch64-asm-2.c: Regenerated. * aarch64-dis-2.c: Regenerated. * aarch64-opc-2.c: Regenerated.
131 lines
5.4 KiB
C
131 lines
5.4 KiB
C
/* aarch64-dis.h -- Header file for aarch64-dis.c and aarch64-dis-2.c.
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Copyright (C) 2012-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef OPCODES_AARCH64_DIS_H
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#define OPCODES_AARCH64_DIS_H
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#include "bfd_stdint.h"
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#include "aarch64-opc.h"
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/* Lookup opcode WORD in the opcode table.
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In the case of multiple aarch64_opcode candidates, one of them will be
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returned; for other candidate(s), call aarch64_find_next_opcode to
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obtain. Note that aarch64_find_next_opcode finds the next
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aarch64_opcode candidate in a way as if all related aarch64_opcode
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entries were in a single-link list.
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N.B. all alias opcodes are ignored here. */
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const aarch64_opcode* aarch64_opcode_lookup (uint32_t);
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const aarch64_opcode* aarch64_find_next_opcode (const aarch64_opcode *);
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/* Given OPCODE, return its alias, e.g. given UBFM, return LSL.
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In the case of multiple alias candidates, the one of the highest priority
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(or one of several aliases of the same highest priority) will be
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returned; for the other candidate(s), call aarch64_find_next_alias_opcode
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to obtain. Note that aarch64_find_next_alias_opcode finds the next
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alias candidate in a way as if all related aliases were in a single-link
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list with priority from the highest to the least. */
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const aarch64_opcode* aarch64_find_alias_opcode (const aarch64_opcode *);
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const aarch64_opcode* aarch64_find_next_alias_opcode (const aarch64_opcode *);
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/* Switch-table-based high-level operand extractor. */
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bfd_boolean
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aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
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const aarch64_insn, const aarch64_inst *,
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aarch64_operand_error *);
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/* Operand extractors. */
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#define AARCH64_DECL_OPD_EXTRACTOR(x) \
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bfd_boolean aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
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const aarch64_insn, const aarch64_inst *, \
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aarch64_operand_error *)
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AARCH64_DECL_OPD_EXTRACTOR (ext_none);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
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AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglane);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_reglist_r);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ldst_elemlist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_shift);
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AARCH64_DECL_OPD_EXTRACTOR (ext_shll_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_half);
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AARCH64_DECL_OPD_EXTRACTOR (ext_advsimd_imm_modified);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fpimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_fbits);
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AARCH64_DECL_OPD_EXTRACTOR (ext_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_inv_limm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_ft);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simple);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_offset);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_regoff);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_simm10);
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AARCH64_DECL_OPD_EXTRACTOR (ext_addr_uimm12);
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AARCH64_DECL_OPD_EXTRACTOR (ext_simd_addr_post);
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AARCH64_DECL_OPD_EXTRACTOR (ext_cond);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
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AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
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AARCH64_DECL_OPD_EXTRACTOR (ext_barrier_dsb_nxs);
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AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
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AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
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AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s9xvl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_u6);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rr_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_rz_xtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zi_u5);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_zero_one);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
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AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
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#undef AARCH64_DECL_OPD_EXTRACTOR
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#endif /* OPCODES_AARCH64_DIS_H */
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