mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
177 lines
4.7 KiB
C
177 lines
4.7 KiB
C
// -*- C -*-
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// Simulator definition for the MIPS MIPS-3D ASE.
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// Copyright (C) 2002-2024 Free Software Foundation, Inc.
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// Contributed by Ed Satterthwaite and Chris Demetriou, of Broadcom
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// Corporation (SiByte).
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// Reference: MIPS64 Architecture for Programmers Volume IV-c:
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// The MIPS-3D Application-Specific Extension to the
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// MIPS64 Architecture. (MIPS Document MD00099)
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010001,10,110,5.FT,5.FS,5.FD,011000:COP1:64,f::ADDR.PS
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"addr.ps f<FD>, f<FS>, f<FT>"
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*mips3d:
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{
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/* fd.PL = ft.PU + ft.PL; fd.PU = fs.PU + fs.PL; */
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_ps, AddR (ValueFPR (FS, fmt_ps),
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ValueFPR (FT, fmt_ps), fmt_ps));
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}
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010001,01001,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY2tf
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"bc1any2%s<TF> <CC>, %#lx<OFFSET>"
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*mips3d:
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{
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address_word offset;
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int cc = CC;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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if ((cc & 0x1) != 0)
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Unpredictable ();
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if ((GETFCC (cc) == TF) || (GETFCC (cc + 1) == TF))
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{
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offset = (EXTEND16 (OFFSET) << 2);
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DELAY_SLOT (NIA + offset);
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}
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}
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010001,01010,3.CC,0,1.TF,16.OFFSET:COP1:64,f::BC1ANY4tf
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"bc1any4%s<TF> <CC>, %#lx<OFFSET>"
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*mips3d:
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{
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address_word offset;
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int cc = CC;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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if ((cc & 0x3) != 0)
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Unpredictable ();
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if ((GETFCC (cc) == TF)
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|| (GETFCC (cc + 1) == TF)
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|| (GETFCC (cc + 2) == TF)
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|| (GETFCC (cc + 3) == TF))
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{
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offset = (EXTEND16 (OFFSET) << 2);
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DELAY_SLOT (NIA + offset);
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}
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}
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010001,10,3.FMT,5.FT,5.FS,3.CC,01,11,4.COND:COP1:64,f::CABS.cond.fmt
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"cabs.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
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*mips3d:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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CompareAbs (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
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TRACE_ALU_RESULT (ValueFCR (31));
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}
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010001,10,110,00000,5.FS,5.FD,100100:COP1:64,f::CVT.PW.PS
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"cvt.pw.ps f<FD>, f<FS>"
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*mips3d:
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{
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/* fd.pu = cvt_rnd (fs.pu); fd.pl = cvt_rnd (fs.pl); */
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/* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word. */
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_pw, ConvertPS (GETRM (), ValueFPR (FS, fmt_ps),
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fmt_ps, fmt_word));
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}
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010001,10,100,00000,5.FS,5.FD,100110:COP1:64,f::CVT.PS.PW
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"cvt.ps.pw f<FD>, f<FS>"
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*mips3d:
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{
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/* fd.pl = cvt_rnd (fs.pl); fd.pu = cvt_rnd (fs.pu); */
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/* fmt_pw is fmt_long for 64 bit transfers, but cvt encoding is fmt_word. */
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_ps, ConvertPS (GETRM (), ValueFPR (FS, fmt_pw),
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fmt_word, fmt_ps));
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}
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010001,10,110,5.FT,5.FS,5.FD,011010:COP1:64,f::MULR.PS
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"mulr.ps f<FD>, f<FS>, f<FT>"
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*mips3d:
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{
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/* fd.PL = ft.PU * ft.PL; fd.PU = fs.PU * fs.PL; */
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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StoreFPR (FD, fmt_ps, MultiplyR (ValueFPR (FS, fmt_ps),
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ValueFPR (FT, fmt_ps), fmt_ps));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,011101:COP1:64,f::RECIP1.fmt
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"recip1.%s<FMT> f<FD>, f<FS>"
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*mips3d:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, Recip1 (ValueFPR (FS, fmt), fmt));
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}
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010001,10,3.FMT,5.FT,5.FS,5.FD,011100:COP1:64,f::RECIP2.fmt
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"recip2.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mips3d:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, Recip2 (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
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}
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010001,10,3.FMT,00000,5.FS,5.FD,011110:COP1:64,f::RSQRT1.fmt
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"rsqrt1.%s<FMT> f<FD>, f<FS>"
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*mips3d:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, RSquareRoot1 (ValueFPR (FS, fmt), fmt));
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}
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010001,10,3.FMT,5.FT,5.FS,5.FD,011111:COP1:64,f::RSQRT2.fmt
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"rsqrt2.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mips3d:
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{
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int fmt = FMT;
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check_fpu (SD_);
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check_u64 (SD_, instruction_0);
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check_fmt_p (SD_, fmt, instruction_0);
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StoreFPR (FD, fmt, RSquareRoot2 (ValueFPR (FS, fmt),
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ValueFPR (FT, fmt), fmt));
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}
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