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2c62985659
binutils:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* readelf.c (print_mips_isa_ext): Print the value of Octeon3.
gas:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3.
(mips_cpu_info_table): Octeon3 enables virt ase.
* doc/c-mips.texi: Document octeon3 as an acceptable value for
-march=.
gas/testsuite:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gas/mips/mips.exp: Add support for Octeon3 architecture.
Also add in support for running Octeon3 tests.
* gas/mips/octeon3.d: New test.
* gas/mips/octeon3.s: New test source.
opcodes:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add octeon3.
* mips-opc.c (IOCT): Include INSN_OCTEON3.
(IOCT2): Likewise.
(IOCT3): New define.
(IVIRT): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti
IVIRT instructions.
Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another
operand for IOCT3.
bfd:
2014-10-31 Andrew Pinski <apinski@cavium.com>
Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* archures.c: Add octeon3 for mips target.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c: Define I_mipsocteon3.
nfo_struct): Add octeon3 support.
* bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for
octeon3.
(mips_set_isa_flags): Add support for octeon3.
(bfd_mips_isa_ext): Add bfd_mach_mips_octeon3.
(mips_mach_extensions): Make bfd_mach_mips_octeon3 an
extension of bfd_mach_mips_octeon2.
(print_mips_isa_ext): Print the value of Octeon3.
167 lines
6.2 KiB
C
167 lines
6.2 KiB
C
/* bfd back-end for mips support
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Copyright (C) 1990-2014 Free Software Foundation, Inc.
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Written by Steve Chamberlain of Cygnus Support.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "bfd.h"
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#include "libbfd.h"
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static const bfd_arch_info_type *mips_compatible
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(const bfd_arch_info_type *, const bfd_arch_info_type *);
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/* The default routine tests bits_per_word, which is wrong on mips as
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mips word size doesn't correlate with reloc size. */
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static const bfd_arch_info_type *
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mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
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{
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if (a->arch != b->arch)
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return NULL;
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/* Machine compatibility is checked in
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_bfd_mips_elf_merge_private_bfd_data. */
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return a;
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}
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#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
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{ \
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BITS_WORD, /* bits in a word */ \
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BITS_ADDR, /* bits in an address */ \
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8, /* 8 bits in a byte */ \
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bfd_arch_mips, \
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NUMBER, \
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"mips", \
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PRINT, \
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3, \
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DEFAULT, \
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mips_compatible, \
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bfd_default_scan, \
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bfd_arch_default_fill, \
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NEXT, \
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}
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enum
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{
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I_mips3000,
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I_mips3900,
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I_mips4000,
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I_mips4010,
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I_mips4100,
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I_mips4111,
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I_mips4120,
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I_mips4300,
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I_mips4400,
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I_mips4600,
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I_mips4650,
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I_mips5000,
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I_mips5400,
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I_mips5500,
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I_mips5900,
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I_mips6000,
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I_mips7000,
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I_mips8000,
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I_mips9000,
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I_mips10000,
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I_mips12000,
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I_mips14000,
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I_mips16000,
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I_mips16,
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I_mips5,
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I_mipsisa32,
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I_mipsisa32r2,
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I_mipsisa32r3,
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I_mipsisa32r5,
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I_mipsisa32r6,
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I_mipsisa64,
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I_mipsisa64r2,
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I_mipsisa64r3,
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I_mipsisa64r5,
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I_mipsisa64r6,
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I_sb1,
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I_loongson_2e,
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I_loongson_2f,
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I_loongson_3a,
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I_mipsocteon,
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I_mipsocteonp,
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I_mipsocteon2,
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I_mipsocteon3,
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I_xlr,
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I_micromips
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
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N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
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N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)),
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N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
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N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)),
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N (64, 64, bfd_mach_mips4111, "mips:4111", FALSE, NN(I_mips4111)),
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N (64, 64, bfd_mach_mips4120, "mips:4120", FALSE, NN(I_mips4120)),
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N (64, 64, bfd_mach_mips4300, "mips:4300", FALSE, NN(I_mips4300)),
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N (64, 64, bfd_mach_mips4400, "mips:4400", FALSE, NN(I_mips4400)),
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N (64, 64, bfd_mach_mips4600, "mips:4600", FALSE, NN(I_mips4600)),
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N (64, 64, bfd_mach_mips4650, "mips:4650", FALSE, NN(I_mips4650)),
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N (64, 64, bfd_mach_mips5000, "mips:5000", FALSE, NN(I_mips5000)),
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N (64, 64, bfd_mach_mips5400, "mips:5400", FALSE, NN(I_mips5400)),
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N (64, 64, bfd_mach_mips5500, "mips:5500", FALSE, NN(I_mips5500)),
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N (64, 32, bfd_mach_mips5900, "mips:5900", FALSE, NN(I_mips5900)),
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N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
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N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
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N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
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N (64, 64, bfd_mach_mips9000, "mips:9000", FALSE, NN(I_mips9000)),
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N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
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N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
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N (64, 64, bfd_mach_mips14000,"mips:14000", FALSE, NN(I_mips14000)),
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N (64, 64, bfd_mach_mips16000,"mips:16000", FALSE, NN(I_mips16000)),
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N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
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N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)),
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N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)),
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N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
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N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", FALSE, NN(I_mipsisa32r3)),
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N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", FALSE, NN(I_mipsisa32r5)),
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N (32, 32, bfd_mach_mipsisa32r6,"mips:isa32r6", FALSE, NN(I_mipsisa32r6)),
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N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
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N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
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N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", FALSE, NN(I_mipsisa64r3)),
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N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)),
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N (64, 64, bfd_mach_mipsisa64r6,"mips:isa64r6", FALSE, NN(I_mipsisa64r6)),
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N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
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N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
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N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
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N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
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N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
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N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
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N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
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N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", FALSE, NN(I_mipsocteon3)),
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N (64, 64, bfd_mach_mips_xlr, "mips:xlr", FALSE, NN(I_xlr)),
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N (64, 64, bfd_mach_mips_micromips,"mips:micromips",FALSE,0)
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};
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/* The default architecture is mips:3000, but with a machine number of
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zero. This lets the linker distinguish between a default setting
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of mips, and an explicit setting of mips:3000. */
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const bfd_arch_info_type bfd_mips_arch =
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N (32, 32, 0, "mips", TRUE, &arch_info_struct[0]);
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