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06c441ccef
2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
69 lines
1.1 KiB
Plaintext
69 lines
1.1 KiB
Plaintext
BC1F,0x45000000
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BEQL,0x50000000
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BGEZAL,0x04310000
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BGEZALL,0x04130000
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BGEZL,0x04030000
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BLTZALL,0x04120000
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BLTZL,0x04020000
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BNEL,0x54000000
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C.DEQ.D,0x44000030
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CACHE,0xbc000000
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CVT.PS.S,0x46000026
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CVT.S.PL,0x46c00028
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CVT.S.PU,0x46c00020
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DCLO,0x70000025
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DCLZ,0x70000024
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LDL,0x68000000
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LDR,0x6c000000
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LDXC1,0x4c000001
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LL,0xc0000000
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LLD,0xd0000000
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LUXC1,0x4c000005
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LWL,0x88000000
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LWLE,0x7c000019
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LWR,0x98000000
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LWRE,0x7c00001a
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LWXC1,0x4c000000
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MADD,0x70000000
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MADD.D,0x4c000020
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MADDU,0x70000001
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MOVF,0x00000001
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MOVF.D,0x44000011
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MOVN.D,0x44000013
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MOVT,0x00010001
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MOVT.D,0x44010011
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MOVZ.D,0x44000012
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MSUB,0x70000004
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MSUB.D,0x4c000028
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MSUBU,0x70000005
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MUL,0x70000002
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NEG.S,0x44000007
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NMADD.D,0x4c000030
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NMSUB.D,0x4c000038
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PLL.PS,0x46c0002c
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PLU.PS,0x46c0002d
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PREF,0xcc000000
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PREFX,0x4c00000f
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PUL.PS,0x46c0005e
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PUU.PS,0x46c0002f
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RINT.fmt,0x4400001a
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SC,0xe0000000
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SCD,0xf0000000
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SDBBP,0x7000003f
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SDL,0xb0000000
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SDR,0xb4000000
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SDXC1,0x4c000009
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SUB.D,0x44000001
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SUXC1,0x4c00000d
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SWL,0xa8000000
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SWLE,0x7c000021
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SWR,0xb8000000
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SWRE,0x7c000022
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SWXC1,0x4c000008
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TEQI,0x040c0000
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TGEI,0x04080000
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TGEIU,0x04090000
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TLTI,0x040a0000
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TLTIU,0x040b0000
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TNEI,0x040c0000
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