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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
198 lines
2.7 KiB
ArmAsm
198 lines
2.7 KiB
ArmAsm
# sh testcase for movua
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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start
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movua_1:
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set_grs_a5a5
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mov.l srcp, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x03020100
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.else
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assertreg0 0x00010203
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x04030201
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.else
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assertreg0 0x01020304
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x05040302
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.else
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assertreg0 0x02030405
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x06050403
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.else
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assertreg0 0x03040506
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x07060504
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.else
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assertreg0 0x04050607
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x08070605
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.else
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assertreg0 0x05060708
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x09080706
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.else
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assertreg0 0x06070809
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0a090807
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.else
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assertreg0 0x0708090a
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0b0a0908
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.else
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assertreg0 0x08090a0b
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0c0b0a09
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.else
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assertreg0 0x090a0b0c
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0d0c0b0a
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.else
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assertreg0 0x0a0b0c0d
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0e0d0c0b
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.else
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assertreg0 0x0b0c0d0e
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.endif
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add #1, r1
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movua.l @r1, r0
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.ifdef LITTLE
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assertreg0 0x0f0e0d0c
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.else
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assertreg0 0x0c0d0e0f
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.endif
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assertreg src+12, r1
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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bra movua_4:
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nop
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.align 0
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src: .byte 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
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.align 2
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srcp: .long src
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movua_4:
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set_grs_a5a5
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mov.l srcp2, r1
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movua.l @r1+, r0
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.ifdef LITTLE
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assertreg0 0x03020100
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.else
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assertreg0 0x00010203
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.endif
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assertreg src+4, r1
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mov.l srcp2, r1
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add #1, r1
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movua.l @r1+, r0
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.ifdef LITTLE
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assertreg0 0x04030201
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.else
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assertreg0 0x01020304
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.endif
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assertreg src+5, r1
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mov.l srcp2, r1
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add #2, r1
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movua.l @r1+, r0
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.ifdef LITTLE
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assertreg0 0x05040302
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.else
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assertreg0 0x02030405
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.endif
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assertreg src+6, r1
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mov.l srcp2, r1
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add #3, r1
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movua.l @r1+, r0
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.ifdef LITTLE
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assertreg0 0x06050403
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.else
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assertreg0 0x03040506
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.endif
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assertreg src+7, r1
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test_gr_a5a5 r2
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test_gr_a5a5 r3
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test_gr_a5a5 r4
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test_gr_a5a5 r5
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test_gr_a5a5 r6
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test_gr_a5a5 r7
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test_gr_a5a5 r8
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test_gr_a5a5 r9
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test_gr_a5a5 r10
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test_gr_a5a5 r11
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test_gr_a5a5 r12
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test_gr_a5a5 r13
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test_gr_a5a5 r14
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pass
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exit 0
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srcp2: .long src
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