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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
1023 lines
20 KiB
ArmAsm
1023 lines
20 KiB
ArmAsm
# Hitachi H8 testcase 'neg.b, neg.w, neg.l'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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# Instructions tested:
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# neg.b rd ; 1 7 8 rd
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# neg.b @erd ; 7 d rd ???? 1 7 8 ignore
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# neg.b @erd+ ; 0 1 7 4 6 c rd 1??? 1 7 8 ignore
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# neg.b @erd- ; 0 1 7 6 6 c rd 1??? 1 7 8 ignore
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# neg.b @+erd ; 0 1 7 5 6 c rd 1??? 1 7 8 ignore
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# neg.b @-erd ; 0 1 7 7 6 c rd 1??? 1 7 8 ignore
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# neg.b @(d:2, erd) ; 0 1 7 01dd 6 8 rd 8 1 7 8 ignore
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# neg.b @(d:16, erd) ; 0 1 7 4 6 e rd 1??? dd:16 1 7 8 ignore
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# neg.b @(d:32, erd) ; 7 8 rd 4 6 a 2 1??? dd:32 1 7 8 ignore
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# neg.b @aa:16 ; 6 a 1 1??? aa:16 1 7 8 ignore
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# neg.b @aa:32 ; 6 a 3 1??? aa:32 1 7 8 ignore
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# word operations
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# long operations
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#
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# Coming soon:
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# neg.b @aa:8 ; 7 f aaaaaaaa 1 7 8 ignore
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#
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.data
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byte_dest: .byte 0xa5
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.align 2
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word_dest: .word 0xa5a5
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.align 4
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long_dest: .long 0xa5a5a5a5
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start
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#
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# Note: apparently carry is set for neg of anything except zero.
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#
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#
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# 8-bit byte operations
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#
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neg_b_reg8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b Rd
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neg r0l ; 8-bit register
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;;; .word 0x1788
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.b #0x5b, r0l ; result of "neg 0xa5"
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beq .Lbrd
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fail
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.Lbrd:
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test_h_gr16 0xa55b r0 ; r0 changed by 'neg'
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.if (sim_cpu) ; non-zero means h8300h, s, or sx
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test_h_gr32 0xa5a5a55b er0 ; er0 changed by 'neg'
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.endif
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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neg_b_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @eRd
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mov #byte_dest, er0
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neg.b @er0 ; register indirect operand
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;;; .word 0x7d00
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;;; .word 0x1780
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest er0 ; er0 still contains address
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cmp.b #0x5b, @er0 ; memory contents changed
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beq .Lbind
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fail
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.Lbind:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @eRd+
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mov #byte_dest, er0 ; register post-increment operand
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neg.b @er0+
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;;; .word 0x0174
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;;; .word 0x6c08
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;;; .word 0x1780
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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test_h_gr32 byte_dest+1 er0 ; er0 contains address plus one
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cmp.b #0xa5, @-er0
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beq .Lbpostinc
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fail
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.Lbpostinc:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @eRd-
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mov #byte_dest, er0 ; register post-decrement operand
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neg.b @er0-
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;;; .word 0x0176
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;;; .word 0x6c08
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;;; .word 0x1780
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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test_h_gr32 byte_dest-1 er0 ; er0 contains address minus one
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cmp.b #0x5b, @+er0
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beq .Lbpostdec
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fail
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.Lbpostdec:
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_rdpreinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @+eRd
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mov #byte_dest-1, er0
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neg.b @+er0 ; reg pre-increment operand
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;;; .word 0x0175
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;;; .word 0x6c08
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;;; .word 0x1780
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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cmp.b #0xa5, @er0
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beq .Lbpreinc
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fail
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.Lbpreinc:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_rdpredec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @-eRd
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mov #byte_dest+1, er0
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neg.b @-er0 ; reg pre-decr operand
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;;; .word 0x0177
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;;; .word 0x6c08
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;;; .word 0x1780
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.b #0x5b, @er0
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beq .Lbpredec
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fail
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.Lbpredec:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_disp2dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @(dd:2, erd)
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mov #byte_dest-1, er0
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neg.b @(1:2, er0) ; reg plus 2-bit displacement
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;;; .word 0x0175
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;;; .word 0x6808
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;;; .word 0x1780
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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cmp.b #0xa5, @+er0
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beq .Lbdisp2
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fail
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.Lbdisp2:
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test_h_gr32 byte_dest er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_disp16dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @(dd:16, erd)
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mov #byte_dest+100, er0
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neg.b @(-100:16, er0) ; reg plus 16-bit displacement
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;;; .word 0x0174
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;;; .word 0x6e08
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;;; .word -100
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;;; .word 0x1780
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.b #0x5b, @byte_dest
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beq .Lbdisp16
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fail
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.Lbdisp16:
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test_h_gr32 byte_dest+100 er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_disp32dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @(dd:32, erd)
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mov #byte_dest-0xfffff, er0
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neg.b @(0xfffff:32, er0) ; reg plus 32-bit displacement
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;;; .word 0x7804
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;;; .word 0x6a28
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;;; .long 0xfffff
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;;; .word 0x1780
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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cmp.b #0xa5, @byte_dest
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beq .Lbdisp32
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fail
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.Lbdisp32:
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test_h_gr32 byte_dest-0xfffff er0 ; er0 contains destination address
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test_gr_a5a5 1 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_abs16dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @aa:16
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neg.b @byte_dest:16 ; 16-bit absolute address
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;;; .word 0x6a18
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;;; .word byte_dest
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;;; .word 0x1780
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.b #0x5b, @byte_dest
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beq .Lbabs16
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fail
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.Lbabs16:
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test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_b_abs32dst:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.b @aa:32
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neg.b @byte_dest:32 ; 32-bit absolute address
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;;; .word 0x6a38
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;;; .long byte_dest
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;;; .word 0x1780
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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cmp.b #0xa5, @byte_dest
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beq .Lbabs32
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fail
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.Lbabs32:
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test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif
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#
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# 16-bit word operations
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#
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.if (sim_cpu) ; any except plain-vanilla h8/300
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neg_w_reg16:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.w Rd
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neg r1 ; 16-bit register operand
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;;; .word 0x1791
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.w #0x5a5b, r1 ; result of "neg 0xa5a5"
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beq .Lwrd
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fail
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.Lwrd:
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test_h_gr32 0xa5a55a5b er1 ; er1 changed by 'neg'
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu == h8sx)
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neg_w_rdind:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.w @eRd
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mov #word_dest, er1
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neg.w @er1 ; register indirect operand
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;;; .word 0x0154
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;;; .word 0x6d18
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;;; .word 0x1790
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.w #0x5a5b, @word_dest ; memory contents changed
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beq .Lwind
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fail
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.Lwind:
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test_h_gr32 word_dest er1 ; er1 still contains address
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_w_rdpostinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.w @eRd+
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mov #word_dest, er1 ; register post-increment operand
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neg.w @er1+
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;;; .word 0x0154
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;;; .word 0x6d18
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;;; .word 0x1790
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test_carry_set ; H=0 N=1 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_set
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cmp.w #0xa5a5, @word_dest
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beq .Lwpostinc
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fail
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.Lwpostinc:
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test_h_gr32 word_dest+2 er1 ; er1 contains address plus two
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_w_rdpostdec:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; neg.w @eRd-
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mov #word_dest, er1
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neg.w @er1-
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;;; .word 0x0156
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;;; .word 0x6d18
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;;; .word 0x1790
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test_carry_set ; H=0 N=0 Z=0 V=0 C=1
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test_ovf_clear
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test_zero_clear
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test_neg_clear
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cmp.w #0x5a5b, @word_dest
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beq .Lwpostdec
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fail
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.Lwpostdec:
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test_h_gr32 word_dest-2 er1 ; er1 contains address minus two
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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neg_w_rdpreinc:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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|
|
;; neg.w @+eRd
|
|
mov #word_dest-2, er1
|
|
neg.w @+er1 ; reg pre-increment operand
|
|
;;; .word 0x0155
|
|
;;; .word 0x6d18
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.w #0xa5a5, @word_dest
|
|
beq .Lwpreinc
|
|
fail
|
|
.Lwpreinc:
|
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_rdpredec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @-eRd
|
|
mov #word_dest+2, er1
|
|
neg.w @-er1 ; reg pre-decr operand
|
|
;;; .word 0x0157
|
|
;;; .word 0x6d18
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.w #0x5a5b, @word_dest
|
|
beq .Lwpredec
|
|
fail
|
|
.Lwpredec:
|
|
test_h_gr32 word_dest er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_disp2dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @(dd:2, erd)
|
|
mov #word_dest-2, er1
|
|
neg.w @(2:2, er1) ; reg plus 2-bit displacement
|
|
;;; .word 0x0155
|
|
;;; .word 0x6918
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.w #0xa5a5, @word_dest
|
|
beq .Lwdisp2
|
|
fail
|
|
.Lwdisp2:
|
|
test_h_gr32 word_dest-2 er1 ; er1 contains address minus one
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_disp16dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @(dd:16, erd)
|
|
mov #word_dest+100, er1
|
|
neg.w @(-100:16, er1) ; reg plus 16-bit displacement
|
|
;;; .word 0x0154
|
|
;;; .word 0x6f18
|
|
;;; .word -100
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.w #0x5a5b, @word_dest
|
|
beq .Lwdisp16
|
|
fail
|
|
.Lwdisp16:
|
|
test_h_gr32 word_dest+100 er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_disp32dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @(dd:32, erd)
|
|
mov #word_dest-0xfffff, er1
|
|
neg.w @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
|
;;; .word 0x7814
|
|
;;; .word 0x6b28
|
|
;;; .long 0xfffff
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.w #0xa5a5, @word_dest
|
|
beq .Lwdisp32
|
|
fail
|
|
.Lwdisp32:
|
|
test_h_gr32 word_dest-0xfffff er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_abs16dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @aa:16
|
|
neg.w @word_dest:16 ; 16-bit absolute address
|
|
;;; .word 0x6b18
|
|
;;; .word word_dest
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.w #0x5a5b, @word_dest
|
|
beq .Lwabs16
|
|
fail
|
|
.Lwabs16:
|
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_w_abs32dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.w @aa:32
|
|
neg.w @word_dest:32 ; 32-bit absolute address
|
|
;;; .word 0x6b38
|
|
;;; .long word_dest
|
|
;;; .word 0x1790
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.w #0xa5a5, @word_dest
|
|
beq .Lwabs32
|
|
fail
|
|
.Lwabs32:
|
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
.endif ; h8sx
|
|
.endif ; h8/300
|
|
|
|
#
|
|
# 32-bit word operations
|
|
#
|
|
|
|
.if (sim_cpu) ; any except plain-vanilla h8/300
|
|
neg_l_reg16:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l eRd
|
|
neg er1 ; 32-bit register operand
|
|
;;; .word 0x17b1
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, er1 ; result of "neg 0xa5a5a5a5"
|
|
beq .Llrd
|
|
fail
|
|
.Llrd:
|
|
test_h_gr32 0x5a5a5a5b er1 ; er1 changed by 'neg'
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
.if (sim_cpu == h8sx)
|
|
neg_l_rdind:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @eRd
|
|
mov #long_dest, er1
|
|
neg.l @er1 ; register indirect operand
|
|
;;; .word 0x0104
|
|
;;; .word 0x6d18
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, @long_dest ; memory contents changed
|
|
beq .Llind
|
|
fail
|
|
.Llind:
|
|
test_h_gr32 long_dest er1 ; er1 still contains address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_rdpostinc:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @eRd+
|
|
mov #long_dest, er1 ; register post-increment operand
|
|
neg.l @er1+
|
|
;;; .word 0x0104
|
|
;;; .word 0x6d18
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
|
beq .Llpostinc
|
|
fail
|
|
.Llpostinc:
|
|
test_h_gr32 long_dest+4 er1 ; er1 contains address plus two
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_rdpostdec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @eRd-
|
|
mov #long_dest, er1
|
|
neg.l @er1-
|
|
;;; .word 0x0106
|
|
;;; .word 0x6d18
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, @long_dest
|
|
beq .Llpostdec
|
|
fail
|
|
.Llpostdec:
|
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus two
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_rdpreinc:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @+eRd
|
|
mov #long_dest-4, er1
|
|
neg.l @+er1 ; reg pre-increment operand
|
|
;;; .word 0x0105
|
|
;;; .word 0x6d18
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
|
beq .Llpreinc
|
|
fail
|
|
.Llpreinc:
|
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_rdpredec:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @-eRd
|
|
mov #long_dest+4, er1
|
|
neg.l @-er1 ; reg pre-decr operand
|
|
;;; .word 0x0107
|
|
;;; .word 0x6d18
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, @long_dest
|
|
beq .Llpredec
|
|
fail
|
|
.Llpredec:
|
|
test_h_gr32 long_dest er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_disp2dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @(dd:2, erd)
|
|
mov #long_dest-4, er1
|
|
neg.l @(4:2, er1) ; reg plus 2-bit displacement
|
|
;;; .word 0x0105
|
|
;;; .word 0x6918
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
|
beq .Lldisp2
|
|
fail
|
|
.Lldisp2:
|
|
test_h_gr32 long_dest-4 er1 ; er1 contains address minus one
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_disp16dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @(dd:16, erd)
|
|
mov #long_dest+100, er1
|
|
neg.l @(-100:16, er1) ; reg plus 16-bit displacement
|
|
;;; .word 0x0104
|
|
;;; .word 0x6f18
|
|
;;; .word -100
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, @long_dest
|
|
beq .Lldisp16
|
|
fail
|
|
.Lldisp16:
|
|
test_h_gr32 long_dest+100 er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_disp32dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @(dd:32, erd)
|
|
mov #long_dest-0xfffff, er1
|
|
neg.l @(0xfffff:32, er1) ; reg plus 32-bit displacement
|
|
;;; .word 0x7894
|
|
;;; .word 0x6b28
|
|
;;; .long 0xfffff
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
|
beq .Lldisp32
|
|
fail
|
|
.Lldisp32:
|
|
test_h_gr32 long_dest-0xfffff er1 ; er1 contains destination address
|
|
test_gr_a5a5 0 ; Make sure other general regs not disturbed
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_abs16dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @aa:16
|
|
neg.l @long_dest:16 ; 16-bit absolute address
|
|
;;; .word 0x0104
|
|
;;; .word 0x6b08
|
|
;;; .word long_dest
|
|
;;; .word 0x17b0
|
|
|
|
test_carry_set ; H=0 N=0 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_clear
|
|
|
|
cmp.l #0x5a5a5a5b, @long_dest
|
|
beq .Llabs16
|
|
fail
|
|
.Llabs16:
|
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
neg_l_abs32dst:
|
|
set_grs_a5a5 ; Fill all general regs with a fixed pattern
|
|
set_ccr_zero
|
|
|
|
;; neg.l @aa:32
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neg.l @long_dest:32 ; 32-bit absolute address
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|
;;; .word 0x0104
|
|
;;; .word 0x6b28
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|
;;; .long long_dest
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;;; .word 0x17b0
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|
|
|
test_carry_set ; H=0 N=1 Z=0 V=0 C=1
|
|
test_ovf_clear
|
|
test_zero_clear
|
|
test_neg_set
|
|
|
|
cmp.l #0xa5a5a5a5, @long_dest
|
|
beq .Llabs32
|
|
fail
|
|
.Llabs32:
|
|
test_gr_a5a5 0 ; Make sure ALL general regs not disturbed
|
|
test_gr_a5a5 1
|
|
test_gr_a5a5 2
|
|
test_gr_a5a5 3
|
|
test_gr_a5a5 4
|
|
test_gr_a5a5 5
|
|
test_gr_a5a5 6
|
|
test_gr_a5a5 7
|
|
|
|
.endif ; h8sx
|
|
.endif ; h8/300
|
|
|
|
pass
|
|
|
|
exit 0
|