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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
123 lines
2.2 KiB
ArmAsm
123 lines
2.2 KiB
ArmAsm
# Hitachi H8 testcase 'jmp'
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# mach(): all
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# as(h8300): --defsym sim_cpu=0
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# as(h8300h): --defsym sim_cpu=1
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# as(h8300s): --defsym sim_cpu=2
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# as(h8sx): --defsym sim_cpu=3
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# ld(h8300h): -m h8300helf
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# ld(h8300s): -m h8300self
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# ld(h8sx): -m h8300sxelf
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.include "testutils.inc"
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.data
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vector_area:
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.fill 0x400, 1, 0
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start
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.if (sim_cpu == h8sx)
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jmp_8:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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mov.l #.Ltgt_8:32, @0x20
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set_ccr_zero
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;; jmp @@aa:8 ; 8-bit displacement
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jmp @@0x20
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fail
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.Ltgt_8:
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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jmp_7: ; vector jump
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mov.l #vector_area, er0
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ldc.l er0, vbr
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set_grs_a5a5
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mov.l #.Ltgt_7:32, @vector_area+0x300
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set_ccr_zero
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jmp @@0x300
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fail
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.Ltgt_7:
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test_cc_clear
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test_grs_a5a5
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stc.l vbr, er0
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test_h_gr32 vector_area, er0
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.endif ; h8sx
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jmp_24:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; jmp @aa:24 ; 24-bit address
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jmp @.Ltgt_24:24
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fail
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.Ltgt_24:
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.if (sim_cpu) ; Non-zero means h8300h, h8300s, or h8sx
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jmp_reg:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; jmp @ern ; register indirect
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mov.l #.Ltgt_reg, er5
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jmp @er5
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fail
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.Ltgt_reg:
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_h_gr32 .Ltgt_reg er5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif ; not h8300
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.if (sim_cpu == h8sx)
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jmp_32:
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set_grs_a5a5 ; Fill all general regs with a fixed pattern
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set_ccr_zero
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;; jmp @aa:32 ; 32-bit address
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; jmp @.Ltgt_32:32 ; NOTE: hard-coded to avoid relaxing
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.word 0x5908
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.long .Ltgt_32
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fail
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.Ltgt_32:
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test_cc_clear
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test_gr_a5a5 0 ; Make sure other general regs not disturbed
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test_gr_a5a5 1
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test_gr_a5a5 2
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test_gr_a5a5 3
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test_gr_a5a5 4
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test_gr_a5a5 5
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test_gr_a5a5 6
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test_gr_a5a5 7
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.endif ; h8sx
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pass
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exit 0
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