mirror of
https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
633 lines
12 KiB
ArmAsm
633 lines
12 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/seq/se_cc2stat_haz/se_cc2stat_haz.dsp
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// Description:
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// Verify CC hazards under the following condition:
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//
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// (1a) cc2stat (that modifies CC) followed by that uses CC
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// (1b) same as (1a) but kill cc2stat instruction in WB
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//
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// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
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// (2b) same as (2a) but kill cc2stat instruction in WB
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//
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// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
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// (3b) same as (3a) but kill cc2stat instruction in WB
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//
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// (4a) cc2stat (that modifies CC) followed by testset
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// (4b) same as (4a) but kill cc2stat instruction in WB
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//
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// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
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// (5b) same as (5a) but kill cc2stat instruction in WB
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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// ----------------------------------------------------------------
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// Include Files
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// ----------------------------------------------------------------
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include(std.inc)
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include(selfcheck.inc)
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include(symtable.inc)
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include(mmrs.inc)
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// ----------------------------------------------------------------
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// Defines
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// ----------------------------------------------------------------
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#ifndef STACKSIZE
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#define STACKSIZE 0x00000010
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#endif
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#ifndef ITABLE
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#define ITABLE CODE_ADDR_1 //
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#endif
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// ----------------------------------------------------------------
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// Reset ISR
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// - set the processor operating modes
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// - initialize registers
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// - etc ...
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// ----------------------------------------------------------------
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RST_ISR:
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// Initialize data registers
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//INIT_R_REGS(0);
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R7 = 0;
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R6 = 0;
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R5 = 0;
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R4 = 0;
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R3 = 0;
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R2 = 0;
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R1 = 0;
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R0 = 0;
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// Initialize pointer registers
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INIT_P_REGS(0);
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// Initialize address registers
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INIT_I_REGS(0);
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INIT_M_REGS(0);
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INIT_L_REGS(0);
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INIT_B_REGS(0);
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// Initialize the address of the checkreg data segment
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// **** THIS IS NEEDED WHENEVER CHECKREG IS USED ****
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CHECK_INIT_DEF(p5); //CHECK_INIT(p5, 0x00BFFFFC);
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// Inhibit events during MMR writes
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CLI R1;
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// Setup user stack
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LD32_LABEL(sp, USTACK);
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USP = SP;
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// Setup kernel stack
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LD32_LABEL(sp, KSTACK);
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// Setup frame pointer
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FP = SP;
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// Setup event vector table
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LD32(p0, EVT0);
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LD32_LABEL(r0, EMU_ISR); // Emulation Handler (EVT0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RST_ISR); // Reset Handler (EVT1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NMI_ISR); // NMI Handler (EVT2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, EXC_ISR); // Exception Handler (EVT3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // EVT4 not used
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LD32_LABEL(r0, HWE_ISR); // HW Error Handler (EVT5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, TMR_ISR); // Timer Handler (EVT6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV7_ISR); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV8_ISR); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV9_ISR); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV10_ISR); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV11_ISR); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV12_ISR); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV13_ISR); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV14_ISR); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, IGV15_ISR); // IVG15 Handler
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[ P0 ++ ] = R0;
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// Set the EVT_OVERRIDE MMR
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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// Disable L1 data cache
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WR_MMR(DMEM_CONTROL, 0x00000000, p0, r0);
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// Mask interrupts (*)
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R1 = -1;
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// Wait for MMR writes to finish
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CSYNC;
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// Re-enable events
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STI R1;
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// Reset accumulator registers
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A0 = 0;
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A1 = 0;
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// Reset loop counters to deterministic values
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R0 = 0 (Z);
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LT0 = R0;
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LB0 = R0;
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LC0 = R0;
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LT1 = R0;
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LB1 = R0;
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LC1 = R0;
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// Reset other internal regs
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ASTAT = R0;
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SYSCFG = R0;
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RETS = R0;
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// Setup the test to run in USER mode
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LD32_LABEL(r0, USER_CODE);
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RETI = R0;
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// Setup the test to run in SUPERVISOR mode
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// Comment the following line for a USER mode test
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JUMP.S SUPERVISOR_CODE;
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RTI;
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SUPERVISOR_CODE:
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// Load IVG15 general handler (Int15) with MAIN_CODE
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LD32_LABEL(p1, MAIN_CODE);
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LD32(p0, EVT15);
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CLI R1;
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[ P0 ] = P1;
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CSYNC;
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STI R1;
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// Take Int15 which branch to MAIN_CODE after RTI
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RAISE 15;
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RTI;
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USER_CODE:
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// Setup the stack pointer and the frame pointer
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LD32_LABEL(sp, USTACK);
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FP = SP;
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JUMP.S MAIN_CODE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// ISR Table
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// ----------------------------------------------------------------
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// ----------------------------------------------------------------
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// EMU ISR
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// ----------------------------------------------------------------
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EMU_ISR :
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RTE;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// NMI ISR
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// ----------------------------------------------------------------
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NMI_ISR :
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RTN;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// EXC ISR
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// ----------------------------------------------------------------
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EXC_ISR :
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RTX;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// HWE ISR
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// ----------------------------------------------------------------
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HWE_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// TMR ISR
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// ----------------------------------------------------------------
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TMR_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV7 ISR
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// ----------------------------------------------------------------
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IGV7_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV8 ISR
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// ----------------------------------------------------------------
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IGV8_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV9 ISR
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// ----------------------------------------------------------------
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IGV9_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV10 ISR
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// ----------------------------------------------------------------
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IGV10_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV11 ISR
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// ----------------------------------------------------------------
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IGV11_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV12 ISR
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// ----------------------------------------------------------------
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IGV12_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV13 ISR
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// ----------------------------------------------------------------
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IGV13_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV14 ISR
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// ----------------------------------------------------------------
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IGV14_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// IGV15 ISR
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// ----------------------------------------------------------------
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IGV15_ISR :
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RTI;
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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.dw 0xFFFF
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// ----------------------------------------------------------------
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// Main Code
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// ----------------------------------------------------------------
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MAIN_CODE:
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// Enable interrupts in SUPERVISOR mode
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// Comment the following line for a USER mode test
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[ -- SP ] = RETI;
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// Start of the program code
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R0 = 0;
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R1 = 1;
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R2 = 2;
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// Verify CC hazards under the following condition:
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//
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// (1a) cc2stat (that modifies CC) followed by that uses CC
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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CC = AV0;
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A0 = BXORSHIFT( A0 , A1, CC );
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R7 = CC; CHECKREG(R7, 0);
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R6 = A0; CHECKREG(R6, 0);
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R6 = A0.X; CHECKREG(R6, 0);
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R7 = A1; CHECKREG(R7, 1);
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R7 = A1.X; CHECKREG(R7, 0);
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// (1b) same as (1a) but kill cc2stat instruction in WB
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A0 = R1;
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A1 = R1;
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CC = R0 < R2;
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EXCPT 3;
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CC = AV0;
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A0 = BXORSHIFT( A0 , A1, CC );
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R7 = CC; CHECKREG(R7, 0);
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R6 = A0; CHECKREG(R6, 3);
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R6 = A0.X; CHECKREG(R6, 0);
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R7 = A1; CHECKREG(R7, 1);
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R7 = A1.X; CHECKREG(R7, 0);
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// (2a) cc2stat (that modifies CC) followed by conditional branch (predicted)
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R3 = 0;
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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CC = AV0;
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IF !CC JUMP INC_R3_TO_10 (BP);
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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INC_R3_TO_10:
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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// (2b) same as (2a) but kill cc2stat instruction in WB
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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EXCPT 3;
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CC = AV0;
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IF !CC JUMP INC_R3_TO_20 (BP);
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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INC_R3_TO_20:
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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R3 += 1;
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// (3a) cc2stat (that modifies CC) followed by conditional branch (mispredicted)
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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CC = AV0;
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IF CC JUMP INC_R3_TO_20 (BP);
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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// (3b) same as (3a) but kill cc2stat instruction in WB
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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EXCPT 3;
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CC = AV0;
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IF CC JUMP INC_R3_TO_20 (BP);
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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R3 += 2;
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CHECKREG(r3, 60);
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dbg_pass;
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// (4a) cc2stat (that modifies CC) followed by testset
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LD32(p0, DATA_ADDR_3); //LD32(p0, 0xff000000);
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LD32(p1, DATA_ADDR_2); //LD32(p1, 0xffe00000);
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[ P0 ] = R0;
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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CC = AV0;
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QUERY_0:
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TESTSET ( P0 );
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IF !CC JUMP QUERY_0;
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[ P0 ] = R1;
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CHECKMEM32(DATA_ADDR_3, 1); //CHECKMEM32(0xff000000, 1);
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[ P0 ] = R0;
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CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0);
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// (4b) same as (4a) but kill cc2stat instruction in WB
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A0 = 0;
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A1 = R1;
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CC = R0 < R2;
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EXCPT 3;
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CC = AV0;
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QUERY_1:
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TESTSET ( P0 );
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IF !CC JUMP QUERY_1;
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[ P0 ] = R2;
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CHECKMEM32(DATA_ADDR_3, 2); //CHECKMEM32(0xff000000, 2);
|
|
[ P0 ] = R0;
|
|
CHECKMEM32(DATA_ADDR_3, 0); //CHECKMEM32(0xff000000, 0);
|
|
|
|
// (5a) cc2stat (that modifies CC) followed by dag instruction that modifies CC
|
|
A0 = 0;
|
|
A1 = R1;
|
|
CC = R0 < R2;
|
|
CC = AV0;
|
|
CC = P0 < P1;
|
|
|
|
// (5b) same as (5a) but kill cc2stat instruction in WB
|
|
A0 = 0;
|
|
A1 = R1;
|
|
CC = R0 < R2;
|
|
EXCPT 3;
|
|
CC = AV0;
|
|
CC = P0 < P1;
|
|
|
|
|
|
END:
|
|
dbg_pass;
|
|
|
|
// ----------------------------------------------------------------
|
|
// Data Segment
|
|
// - define kernel and user stacks
|
|
// ----------------------------------------------------------------
|
|
|
|
.data
|
|
DATA:
|
|
.space (STACKSIZE);
|
|
|
|
.space (STACKSIZE);
|
|
KSTACK:
|
|
|
|
.space (STACKSIZE);
|
|
USTACK:
|