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https://sourceware.org/git/binutils-gdb.git
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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
263 lines
4.9 KiB
ArmAsm
263 lines
4.9 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/debug/dbg_tr_tbuf0/dbg_tr_tbuf0.dsp
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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include(std.inc)
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include(mmrs.inc)
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include(selfcheck.inc)
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#ifndef ITABLE
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#define ITABLE 0xF0000000
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#endif
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// This test embeds .text offsets, so pad our test so it lines up.
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.space 0x64
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// Boot code
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BOOT :
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INIT_R_REGS(0); // Initialize Dregs
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INIT_P_REGS(0); // Initialize Pregs
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CHECK_INIT(p5, 0x00BFFFFC);
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LD32(p0, EVT0); // Setup Event Vectors and Handlers
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LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
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[ P0 ++ ] = R0;
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[ P0 ++ ] = R0; // IVT4 not used
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LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I10HANDLE); // IVG10 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I11HANDLE); // IVG11 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I12HANDLE); // IVG12 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I13HANDLE); // IVG13 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I14HANDLE); // IVG14 Handler
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[ P0 ++ ] = R0;
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LD32_LABEL(r0, I15HANDLE); // IVG15 Handler
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[ P0 ++ ] = R0;
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LD32(p0, EVT_OVERRIDE);
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R0 = 0;
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[ P0 ++ ] = R0;
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R0 = -1; // Change this to mask interrupts (*)
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[ P0 ] = R0; // IMASK
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LD32_LABEL(p1, START);
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LD32(p0, EVT15);
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[ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
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LD32_LABEL(r7, DUMMY);
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RETI = r7;
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RAISE 15; // after we RTI, INT 15 should be taken
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NOP; // Workaround for Bug 217
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RTI;
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NOP;
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NOP;
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NOP;
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DUMMY:
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NOP;
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NOP;
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NOP;
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NOP;
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START :
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WR_MMR(TBUFCTL, 0x00000001, p0, r0); // Turn ON trace Buffer
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WR_MMR(TBUFCTL, 0x0000000b, p0, r0); // Turn ON trace Buffer
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// TBUFPWR = 1
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// TBUFEN = 1
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// TBUFOVF = 0
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// CMPLP = 01
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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R6 = 0;
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R7 = 10;
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JMP:
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JUMP.S LABEL0;
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NOP;
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NOP;
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LABEL0:
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P1 = 0x0006;
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JUMP (PC+P1);
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LABEL1:
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LD32(R3, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
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LABEL2:
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CC = R7 == R6;
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IF CC JUMP END;
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R6 += 1;
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JUMP LABEL2;
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LABEL3:
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NOP;
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LABEL4:
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LD32(R4, 0xBADD); //<< WARNING: LINE MAY NEED MANUAL TRANSLATION >>
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END:
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R0 = 1;
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NOP;
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NOP;
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NOP;
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CHECKREG(r3, 0x00000000);
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CHECKREG(r4, 0x00000000);
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// Read the contents of the Trace Buffer
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RD_MMR(TBUFSTAT, p0, r0);
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CHECKREG(r0, 0x00000004);
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// Read last entry of the Trace Buffer
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RD_MMR(TBUF, p0, r1);
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CHECKREG(r1, 0x00000256);
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RD_MMR(TBUF, p0, r2);
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CHECKREG(r2, 0x00000246);
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RD_MMR(TBUFSTAT, p0, r0);
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CHECKREG(r0, 0x00000003);
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// Read last entry of the Trace Buffer
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RD_MMR(TBUF, p0, r1);
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CHECKREG(r1, 0x00000245);
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RD_MMR(TBUF, p0, r2);
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CHECKREG(r2, 0x0000024a);
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RD_MMR(TBUFSTAT, p0, r0);
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CHECKREG(r0, 0x00000002);
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// Read last entry of the Trace Buffer
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RD_MMR(TBUF, p0, r1);
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CHECKREG(r1, 0x00000240);
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RD_MMR(TBUF, p0, r2);
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CHECKREG(r2, 0x0000023a);
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RD_MMR(TBUFSTAT, p0, r0);
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CHECKREG(r0, 0x00000001);
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// Read last entry of the Trace Buffer
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RD_MMR(TBUF, p0, r1);
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CHECKREG(r1, 0x00000238);
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RD_MMR(TBUF, p0, r2);
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CHECKREG(r2, 0x00000232);
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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NOP;
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dbg_pass; // Call Endtest Macro
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//*********************************************************************
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//
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// Handlers for Events
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//
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EHANDLE: // Emulation Handler 0
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RTE;
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RHANDLE: // Reset Handler 1
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RTI;
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NHANDLE: // NMI Handler 2
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RTN;
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XHANDLE: // Exception Handler 3
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RTX;
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NOP;NOP;NOP;NOP;NOP;
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NOP;NOP;NOP;NOP;NOP;
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HWHANDLE: // HW Error Handler 5
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RTI;
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THANDLE: // Timer Handler 6
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RTI;
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I7HANDLE: // IVG 7 Handler
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RTI;
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I8HANDLE: // IVG 8 Handler
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RTI;
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I9HANDLE: // IVG 9 Handler
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RTI;
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I10HANDLE: // IVG 10 Handler
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RTI;
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I11HANDLE: // IVG 11 Handler
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RTI;
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I12HANDLE: // IVG 12 Handler
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RTI;
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I13HANDLE: // IVG 13 Handler
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RTI;
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I14HANDLE: // IVG 14 Handler
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RTI;
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I15HANDLE: // IVG 15 Handler
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RTI;
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