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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
119 lines
2.8 KiB
ArmAsm
119 lines
2.8 KiB
ArmAsm
//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
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// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
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# mach: bfin
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.include "testutils.inc"
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start
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imm32 r0, 0xa08d2311;
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imm32 r1, 0x10120040;
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imm32 r2, 0x62b61557;
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imm32 r3, 0x07300007;
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imm32 r4, 0x00740088;
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imm32 r5, 0x609950aa;
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imm32 r6, 0x20bb06cc;
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imm32 r7, 0xd90e108f;
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imm32 p1, 0x1401101f;
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imm32 p2, 0x3204108e;
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imm32 p3, 0xd93f1084;
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imm32 p4, 0xeb04106f;
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imm32 p5, 0xa90e5089;
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ASTAT = R0;
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CC = R1; // cc2dreg
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R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L; // dsp32mac
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I0 = P1; // regmv
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IF CC R1 = R3; // ccmov
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CC = ! CC; // cc2dreg
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R4.H = R1.L + R0.L (S); // dsp32alu
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M0 = P2; // regmv
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IF CC R3 = R2; // ccmov
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CC = R0 < R1; // ccflag
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R4.L = R5.L << 1; // dsp32shiftimm
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I0 += M0; // dagmodim
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R2 = R0 + R2; // comp3op dr plus dr
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IF CC R4 = R5; // ccmov
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CC = R2 == R3; // ccflag
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R7 = R1.L * R4.L, R6 = R1.H * R4.H; // dsp32mult
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R5 = R0 + R2; // comp3op dr plus dr
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BITCLR( R6 , 1 );
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IF CC R4 = R5; // ccmov
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CC = R0; // cc2dreg
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A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac
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IF !CC JUMP LABEL1; // branch on
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CC = ! CC; // cc2dreg
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P1.L = 0x3000; // ldimmhalf
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A0 += A1 (W32); // dsp32alu a0 + a1
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IF !CC JUMP LABEL2 (BP); // branch
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LABEL1:
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R6 = R6 + R2;
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JUMP.S END;
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LABEL2:
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R7 = R5 - R7;
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CC = R0 < R1; // ccflag
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P2 = A0.w;
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IF CC JUMP END (BP); // branch
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P3 = A1.w;
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R5 = R5 + R7;
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END:
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CHECKREG r0, 0xA08D2311;
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CHECKREG r1, 0x07300007;
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CHECKREG r2, 0xA08E3868;
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CHECKREG r3, 0x07300007;
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CHECKREG r4, 0x609950AA;
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CHECKREG r5, 0x411B5B79;
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CHECKREG r6, 0x056C9760;
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CHECKREG r7, 0x4116F22D;
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CHECKREG p1, 0x14013000;
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CHECKREG p2, 0x033352A4;
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CHECKREG p3, 0xD93F1084;
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imm32 r0, 0x408d2711;
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imm32 r1, 0x15124040;
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imm32 r2, 0x62661557;
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imm32 r3, 0x073b0007;
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imm32 r4, 0x01f49088;
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imm32 r5, 0x6e2959aa;
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imm32 r6, 0xa0b506cc;
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imm32 r7, 0x00000002;
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CC = R1; // cc2dreg
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P1 = -15; // compi2opp_pr_eq_i7
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R2 = ROT R2 BY 1; // dsp32shiftim_rot
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CC = ! CC; // cc2dreg
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R3 >>= R7; // alu2op sft
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R4 = ROT R0 BY -3; // dsp32shiftim_rot
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CC = R0 < R1; // ccflag
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R3 = ( A1 = R7.L * R4.L ), R2 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair
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R5 = R0 + R2; // comp3op dr plus dr
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R6 = ROT R4 BY 5; // dsp32shiftim_rot
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CC = R2 == R3; // ccflag
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P2 = R1; // regmv
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R4.H = R1.L + R3.H (S); // dsp32alu
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I0 = P1; // regmv
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IF CC R4 = R5; // ccmov
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CC = R0; // cc2dreg
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R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft
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I0 += 2;
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P3 = I0;
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R3.L = R5.L << 1; // dsp32shiftimm
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R7 = ROT R6 BY R7.L; // dsp32shiftim_rot
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CHECKREG r0, 0x408D2711;
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CHECKREG r1, 0x2ACFF368;
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CHECKREG r2, 0x00000000;
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CHECKREG r3, 0xFFFD4E22;
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CHECKREG r4, 0x403DA4E2;
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CHECKREG r5, 0x408D2711;
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CHECKREG r6, 0x15BD33A8;
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CHECKREG r7, 0x56F4CEA2;
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CHECKREG p1, 0xFFFFFFF1;
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CHECKREG p2, 0x15124040;
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CHECKREG p3, 0xFFFFFFF3;
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pass
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