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https://sourceware.org/git/binutils-gdb.git
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252dcdf432
ppc64 ld optimises sequences like the following addis 3,13,wot@tprel@ha lwz 3,wot@tprel@l(3) to nop lwz 3,wot@tprel(13) when "wot" is located near enough to the thread pointer. However, the ABI doesn't require that R_PPC64_TPREL16_HA always be on an addis rt,13,imm instruction, and while ld checked for that on the high-part instruction it didn't disable the optimisation on the low-part instruction. This patch fixes that problem, disabling the tprel optimisation globally if high-part instructions don't pass sanity checks. The optimisation is also enabled for ppc32, where before ld.bfd had the code in the wrong place and ld.gold had it in a block only enabled for ppc64. bfd/ * elf32-ppc.c (ppc_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc_elf_relocate_section): Move TPREL16_HA/LO optimisation later. Don't sanity check them here. * elf64-ppc.c (ppc64_elf_check_relocs): Set has_tls_reloc for high part tprel16 relocs. (ppc64_elf_tls_optimize): Sanity check high part tprel16 relocs. Clear do_tls_opt on odd instructions. (ppc64_elf_relocate_section): Don't sanity check TPREL16_HA. ld/ * testsuite/ld-powerpc/tls32.d: Update for TPREL_HA/LO optimisation. * testsuite/ld-powerpc/tlsexe32.d: Likewise. * testsuite/ld-powerpc/tlsldopt32.d: Likewise. * testsuite/ld-powerpc/tlsmark32.d: Likewise. * testsuite/ld-powerpc/tlsopt4_32.d: Likewise. * testsuite/ld-powerpc/tprel.s, * testsuite/ld-powerpc/tprel.d, * testsuite/ld-powerpc/tprel32.d: New tests. * testsuite/ld-powerpc/tprelbad.s, * testsuite/ld-powerpc/tprelbad.d: New test. * testsuite/ld-powerpc/powerpc.exp: Run them. gold/ * powerpc.cc (Target_powerpc): Add tprel_opt_ and accessors. (Target_powerpc::Scan::local): Sanity check tprel high relocs. (Target_powerpc::Scan::global): Likewise. (Target_powerpc::Relocate::relocate): Control tprel optimisation with tprel_opt_ and enable for 32-bit.
76 lines
2.9 KiB
Makefile
76 lines
2.9 KiB
Makefile
#source: tls32.s
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#as: -a32
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#ld: tmpdir/libtlslib32.so
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#objdump: -dr
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#target: powerpc*-*-*
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.*
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Disassembly of section \.text:
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.* <_start>:
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.*: (42 9f 00 05|05 00 9f 42) bcl 20,4\*cr7\+so,.* <_start\+0x4>
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.*: (7f c8 02 a6|a6 02 c8 7f) mflr r30
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.*: (3f de 00 02|02 00 de 3f) addis r30,r30,2
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.*: (3b de 81 08|08 81 de 3b) addi r30,r30,-32504
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.*: (80 7f ff f4|f4 ff 7f 80) lwz r3,-12\(r31\)
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.*: (7c 63 12 14|14 12 63 7c) add r3,r3,r2
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.*: (38 7f ff f8|f8 ff 7f 38) addi r3,r31,-8
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.*: (48 00 00 65|65 00 00 48) bl .* <__tls_get_addr_opt@plt>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 90 1c|1c 90 62 38) addi r3,r2,-28644
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096
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.*: (39 23 80 20|20 80 23 39) addi r9,r3,-32736
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (81 49 80 24|24 80 49 81) lwz r10,-32732\(r9\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (a1 42 90 2c|2c 90 42 a1) lhz r10,-28628\(r2\)
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.*: (89 42 90 30|30 90 42 89) lbz r10,-28624\(r2\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (99 42 90 34|34 90 42 99) stb r10,-28620\(r2\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 90 00|00 90 62 38) addi r3,r2,-28672
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 10 00|00 10 62 38) addi r3,r2,4096
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.*: (91 43 80 04|04 80 43 91) stw r10,-32764\(r3\)
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.*: (3d 23 00 00|00 00 23 3d) addis r9,r3,0
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.*: (91 49 80 08|08 80 49 91) stw r10,-32760\(r9\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (b1 42 90 2c|2c 90 42 b1) sth r10,-28628\(r2\)
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.*: (a1 42 90 14|14 90 42 a1) lhz r10,-28652\(r2\)
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (a9 42 90 18|18 90 42 a9) lha r10,-28648\(r2\)
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.* <__tls_get_addr_opt@plt>:
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.*: (81 63 00 00|00 00 63 81) lwz r11,0\(r3\)
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.*: (81 83 00 04|04 00 83 81) lwz r12,4\(r3\)
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.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
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.*: (2c 0b 00 00|00 00 0b 2c) cmpwi r11,0
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.*: (7c 6c 12 14|14 12 6c 7c) add r3,r12,r2
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.*: (4d 82 00 20|20 00 82 4d) beqlr
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.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (3d 60 01 81|81 01 60 3d) lis r11,385
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.*: (81 6b 03 94|94 03 6b 81) lwz r11,916\(r11\)
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.*: (7d 69 03 a6|a6 03 69 7d) mtctr r11
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <__glink(_PLTresolve)?>:
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.*: (3d 80 01 81|81 01 80 3d) lis r12,385
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.*: (3d 6b fe 80|80 fe 6b 3d) addis r11,r11,-384
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.*: (80 0c 03 8c|8c 03 0c 80) lwz r0,908\(r12\)
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.*: (39 6b fd 90|90 fd 6b 39) addi r11,r11,-624
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.*: (7c 09 03 a6|a6 03 09 7c) mtctr r0
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.*: (7c 0b 5a 14|14 5a 0b 7c) add r0,r11,r11
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.*: (81 8c 03 90|90 03 8c 81) lwz r12,912\(r12\)
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (60 00 00 00|00 00 00 60) nop
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