mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-03 04:12:10 +08:00
5499c7c71c
PR 20744 bfd/ * elf32-ppc.c (ppc_elf_howto_raw): Correct dst_mask on all VLE 16D relocations. (ppc_elf_vle_split16): Correct field mask and shift for 16D relocs. (ppc_elf_relocate_section): Correct calculation for VLE SDAREL relocs. ld/ * testsuite/ld-powerpc/vle-reloc-2.s: Use r6 for last insn of each group. * testsuite/ld-powerpc/vle-reloc-2.d: Update for above change and sdarel reloc fix.
88 lines
2.6 KiB
Makefile
88 lines
2.6 KiB
Makefile
.*: file format .*
|
|
|
|
Disassembly of section .text:
|
|
|
|
.* <sub1>:
|
|
.*: 00 04 se_blr
|
|
.* <sub2>:
|
|
.*: 00 04 se_blr
|
|
.* <vle_reloc_2>:
|
|
.*: 70 20 c1 a2 e_or2i r1,418
|
|
.*: 70 40 c1 81 e_or2i r2,385
|
|
.*: 70 60 c1 81 e_or2i r3,385
|
|
.*: 70 90 c0 00 e_or2i r4,32768
|
|
.*: 70 bf c7 ff e_or2i r5,65535
|
|
.*: 70 c0 c0 00 e_or2i r6,0
|
|
.*: 70 20 c9 a2 e_and2i\. r1,418
|
|
.*: 70 40 c9 81 e_and2i\. r2,385
|
|
.*: 70 60 c9 81 e_and2i\. r3,385
|
|
.*: 70 90 c8 00 e_and2i\. r4,32768
|
|
.*: 70 bf cf ff e_and2i\. r5,65535
|
|
.*: 70 c0 c8 00 e_and2i\. r6,0
|
|
.*: 70 20 d1 a2 e_or2is r1,418
|
|
.*: 70 40 d1 81 e_or2is r2,385
|
|
.*: 70 60 d1 81 e_or2is r3,385
|
|
.*: 70 90 d0 00 e_or2is r4,32768
|
|
.*: 70 bf d7 ff e_or2is r5,65535
|
|
.*: 70 c0 d0 00 e_or2is r6,0
|
|
.*: 70 20 e1 a2 e_lis r1,418
|
|
.*: 70 40 e1 81 e_lis r2,385
|
|
.*: 70 60 e1 81 e_lis r3,385
|
|
.*: 70 90 e0 00 e_lis r4,32768
|
|
.*: 70 bf e7 ff e_lis r5,65535
|
|
.*: 70 c0 e0 00 e_lis r6,0
|
|
.*: 70 20 e9 a2 e_and2is\. r1,418
|
|
.*: 70 40 e9 81 e_and2is\. r2,385
|
|
.*: 70 60 e9 81 e_and2is\. r3,385
|
|
.*: 70 90 e8 00 e_and2is\. r4,32768
|
|
.*: 70 bf ef ff e_and2is\. r5,65535
|
|
.*: 70 c0 e8 00 e_and2is\. r6,0
|
|
.*: 70 01 99 a2 e_cmp16i r1,418
|
|
.*: 70 02 99 81 e_cmp16i r2,385
|
|
.*: 70 03 99 81 e_cmp16i r3,385
|
|
.*: 72 04 98 00 e_cmp16i r4,-32768
|
|
.*: 73 e5 9f ff e_cmp16i r5,-1
|
|
.*: 70 06 98 00 e_cmp16i r6,0
|
|
.*: 70 01 a9 a2 e_cmpl16i r1,418
|
|
.*: 70 02 a9 81 e_cmpl16i r2,385
|
|
.*: 70 03 a9 81 e_cmpl16i r3,385
|
|
.*: 72 04 a8 00 e_cmpl16i r4,32768
|
|
.*: 73 e5 af ff e_cmpl16i r5,65535
|
|
.*: 70 06 a8 00 e_cmpl16i r6,0
|
|
.*: 70 01 b1 a2 e_cmph16i r1,418
|
|
.*: 70 02 b1 81 e_cmph16i r2,385
|
|
.*: 70 03 b1 81 e_cmph16i r3,385
|
|
.*: 72 04 b0 00 e_cmph16i r4,-32768
|
|
.*: 73 e5 b7 ff e_cmph16i r5,-1
|
|
.*: 70 06 b0 00 e_cmph16i r6,0
|
|
.*: 70 01 b9 a2 e_cmphl16i r1,418
|
|
.*: 70 02 b9 81 e_cmphl16i r2,385
|
|
.*: 70 03 b9 81 e_cmphl16i r3,385
|
|
.*: 72 04 b8 00 e_cmphl16i r4,32768
|
|
.*: 73 e5 bf ff e_cmphl16i r5,65535
|
|
.*: 70 06 b8 00 e_cmphl16i r6,0
|
|
.*: 70 01 89 a2 e_add2i\. r1,418
|
|
.*: 70 02 89 81 e_add2i\. r2,385
|
|
.*: 70 03 89 81 e_add2i\. r3,385
|
|
.*: 72 04 88 00 e_add2i. r4,-32768
|
|
.*: 73 e5 8f ff e_add2i. r5,-1
|
|
.*: 70 06 88 00 e_add2i. r6,0
|
|
.*: 70 01 91 a2 e_add2is r1,418
|
|
.*: 70 02 91 81 e_add2is r2,385
|
|
.*: 70 03 91 81 e_add2is r3,385
|
|
.*: 72 04 90 00 e_add2is r4,-32768
|
|
.*: 73 e5 97 ff e_add2is r5,-1
|
|
.*: 70 06 90 00 e_add2is r6,0
|
|
.*: 70 01 a1 a2 e_mull2i r1,418
|
|
.*: 70 02 a1 81 e_mull2i r2,385
|
|
.*: 70 03 a1 81 e_mull2i r3,385
|
|
.*: 72 04 a0 00 e_mull2i r4,-32768
|
|
.*: 73 e5 a7 ff e_mull2i r5,-1
|
|
.*: 70 06 a0 00 e_mull2i r6,0
|
|
.* <sub3>:
|
|
.*: 00 04 se_blr
|
|
.* <sub4>:
|
|
.*: 00 04 se_blr
|
|
.* <sub5>:
|
|
.*: 00 04 se_blr
|