mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-03 04:12:10 +08:00
e6cfa893f4
On top of prior similar work more opportunities have appeared in the
meantime. Note that this also happens to address the prior lack of
decoding of EVEX.L'L for VMOV{L,H}P{S,D} and VMOV{LH,HL}PS.
500 lines
13 KiB
C
500 lines
13 KiB
C
/* PREFIX_EVEX_0F5B */
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{
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{ VEX_W_TABLE (EVEX_W_0F5B_P_0) },
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{ "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
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{ "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_0F6F */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F6F_P_3) },
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},
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/* PREFIX_EVEX_0F70 */
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{
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{ Bad_Opcode },
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{ "vpshufhw", { XM, EXx, Ib }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F70_P_2) },
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{ "vpshuflw", { XM, EXx, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F78 */
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{
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{ VEX_W_TABLE (EVEX_W_0F78_P_0) },
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{ "vcvttss2usi", { Gdq, EXd, EXxEVexS }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F78_P_2) },
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{ "vcvttsd2usi", { Gdq, EXq, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_0F79 */
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{
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{ VEX_W_TABLE (EVEX_W_0F79_P_0) },
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{ "vcvtss2usi", { Gdq, EXd, EXxEVexR }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F79_P_2) },
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{ "vcvtsd2usi", { Gdq, EXq, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_0F7A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F7A_P_3) },
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},
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/* PREFIX_EVEX_0F7B */
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{
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{ Bad_Opcode },
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{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
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{ "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* PREFIX_EVEX_0F7E */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7E_P_1) },
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{ VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
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},
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/* PREFIX_EVEX_0F7F */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_2) },
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{ VEX_W_TABLE (EVEX_W_0F7F_P_3) },
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},
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/* PREFIX_EVEX_0FC2 */
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{
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{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
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{ "vcmps%XS", { MaskG, VexScalar, EXd, EXxEVexS, CMP }, 0 },
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{ "vcmppX", { MaskG, Vex, EXx, EXxEVexS, CMP }, PREFIX_OPCODE },
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{ "vcmps%XD", { MaskG, VexScalar, EXq, EXxEVexS, CMP }, 0 },
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},
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/* PREFIX_EVEX_0FE6 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0FE6_P_1) },
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{ "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
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{ "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_0F3810 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3810_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3810_P_2) },
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},
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/* PREFIX_EVEX_0F3811 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3811_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3811_P_2) },
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},
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/* PREFIX_EVEX_0F3812 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3812_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3812_P_2) },
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},
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/* PREFIX_EVEX_0F3813 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3813_P_1) },
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{ "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_0F3814 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3814_P_1) },
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{ "vprorv%DQ", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3815 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3815_P_1) },
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{ "vprolv%DQ", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3820 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3820_P_1) },
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{ "vpmovsxbw", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3821 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3821_P_1) },
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{ "vpmovsxbd", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3822 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3822_P_1) },
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{ "vpmovsxbq", { XM, EXxmmdw }, 0 },
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},
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/* PREFIX_EVEX_0F3823 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3823_P_1) },
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{ "vpmovsxwd", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3824 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3824_P_1) },
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{ "vpmovsxwq", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3825 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3825_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3825_P_2) },
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},
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/* PREFIX_EVEX_0F3826 */
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{
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{ Bad_Opcode },
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{ "vptestnm%BW", { MaskG, Vex, EXx }, 0 },
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{ "vptestm%BW", { MaskG, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3827 */
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{
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{ Bad_Opcode },
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{ "vptestnm%DQ", { MaskG, Vex, EXx }, 0 },
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{ "vptestm%DQ", { MaskG, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3828 */
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{
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{ Bad_Opcode },
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{ MOD_TABLE (MOD_EVEX_0F3828_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3828_P_2) },
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},
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/* PREFIX_EVEX_0F3829 */
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{
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{ Bad_Opcode },
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{ "vpmov%BW2m", { MaskG, EXx }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F3829_P_2) },
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},
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/* PREFIX_EVEX_0F382A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F382A_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F382A_P_2) },
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},
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/* PREFIX_EVEX_0F3830 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3830_P_1) },
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{ "vpmovzxbw", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3831 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3831_P_1) },
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{ "vpmovzxbd", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3832 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3832_P_1) },
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{ "vpmovzxbq", { XM, EXxmmdw }, 0 },
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},
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/* PREFIX_EVEX_0F3833 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3833_P_1) },
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{ "vpmovzxwd", { XM, EXxmmq }, 0 },
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},
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/* PREFIX_EVEX_0F3834 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3834_P_1) },
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{ "vpmovzxwq", { XM, EXxmmqd }, 0 },
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},
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/* PREFIX_EVEX_0F3835 */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F3835_P_1) },
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{ VEX_W_TABLE (EVEX_W_0F3835_P_2) },
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},
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/* PREFIX_EVEX_0F3838 */
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{
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{ Bad_Opcode },
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{ MOD_TABLE (MOD_EVEX_0F3838_P_1) },
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{ "vpminsb", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3839 */
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{
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{ Bad_Opcode },
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{ "vpmov%DQ2m", { MaskG, EXx }, 0 },
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{ "vpmins%DQ", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F383A */
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{
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F383A_P_1) },
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{ "vpminuw", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_EVEX_0F3852 */
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{
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{ Bad_Opcode },
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{ "vdpbf16p%XS", { XM, Vex, EXx }, 0 },
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{ "vpdpwssd", { XM, Vex, EXx }, 0 },
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{ "vp4dpwssd", { XM, Vex, EXxmm }, 0 },
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},
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/* PREFIX_EVEX_0F3853 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vpdpwssds", { XM, Vex, EXx }, 0 },
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{ "vp4dpwssds", { XM, Vex, EXxmm }, 0 },
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},
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/* PREFIX_EVEX_0F3868 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vp2intersect%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_0F3872 */
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{
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{ Bad_Opcode },
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{ "vcvtnep%XS2bf16%XY", { XMxmmq, EXx }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F3872_P_2) },
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{ "vcvtne2p%XS2bf16", { XM, Vex, EXx}, 0 },
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},
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/* PREFIX_EVEX_0F389A */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vfmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
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{ "v4fmaddps", { XM, Vex, Mxmm }, 0 },
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},
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/* PREFIX_EVEX_0F389B */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
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{ "v4fmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
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},
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/* PREFIX_EVEX_0F38AA */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vfmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
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{ "v4fnmaddps", { XM, Vex, Mxmm }, 0 },
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},
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/* PREFIX_EVEX_0F38AB */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
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{ "v4fnmaddss", { XMScalar, VexScalar, Mxmm }, 0 },
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},
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/* PREFIX_EVEX_0F3A08 */
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{
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{ "vrndscalep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vrndscalep%XS", { XM, EXx, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A0A */
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{
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{ "vrndscales%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vrndscales%XS", { XMScalar, VexScalar, EXd, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A26 */
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{
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{ "vgetmantp%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vgetmantp%XW", { XM, EXx, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A27 */
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{
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{ "vgetmants%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A56 */
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{
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{ "vreducep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vreducep%XW", { XM, EXx, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A57 */
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{
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{ "vreduces%XH", { XMScalar, VexScalar, EXw, EXxEVexS, Ib }, 0 },
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{ Bad_Opcode },
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{ "vreduces%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A66 */
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{
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{ "vfpclassp%XH%XZ", { MaskG, EXxh, Ib }, 0 },
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{ Bad_Opcode },
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{ "vfpclassp%XW%XZ", { MaskG, EXx, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3A67 */
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{
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{ "vfpclasss%XH", { MaskG, EXw, Ib }, 0 },
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{ Bad_Opcode },
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{ "vfpclasss%XW", { MaskG, EXdq, Ib }, 0 },
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},
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/* PREFIX_EVEX_0F3AC2 */
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{
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{ "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
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{ "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 },
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},
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/* PREFIX_EVEX_MAP5_10 */
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{
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{ Bad_Opcode },
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{ "vmovs%XH", { XMScalar, VexScalarR, EXw }, 0 },
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},
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/* PREFIX_EVEX_MAP5_11 */
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{
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{ Bad_Opcode },
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{ "vmovs%XH", { EXwS, VexScalarR, XMScalar }, 0 },
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},
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/* PREFIX_EVEX_MAP5_1D */
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{
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{ "vcvtss2s%XH", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
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{ Bad_Opcode },
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{ "vcvtps2p%XHx%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_2A */
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{
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{ Bad_Opcode },
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{ "vcvtsi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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},
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/* PREFIX_EVEX_MAP5_2C */
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{
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{ Bad_Opcode },
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{ "vcvttsh2si", { Gdq, EXw, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_MAP5_2D */
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{
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{ Bad_Opcode },
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{ "vcvtsh2si", { Gdq, EXw, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_2E */
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{
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{ "vucomis%XH", { XMScalar, EXw, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_MAP5_2F */
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{
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{ "vcomis%XH", { XMScalar, EXw, EXxEVexS }, 0 },
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},
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/* PREFIX_EVEX_MAP5_51 */
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{
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{ "vsqrtp%XH", { XM, EXxh, EXxEVexR }, 0 },
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{ "vsqrts%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_58 */
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{
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{ "vaddp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
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{ "vadds%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_59 */
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{
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{ "vmulp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
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{ "vmuls%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_5A */
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{
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{ "vcvtp%XH2pd", { XM, EXxmmqdh, EXxEVexS }, 0 },
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{ "vcvts%XH2sd", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
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{ "vcvtp%XD2ph%XZ", { XMM, EXx, EXxEVexR }, 0 },
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{ "vcvts%XD2sh", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
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},
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/* PREFIX_EVEX_MAP5_5B */
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{
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{ VEX_W_TABLE (EVEX_W_MAP5_5B_P_0) },
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{ "vcvttp%XH2dq", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
{ "vcvtp%XH2dq", { XM, EXxmmqh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5C */
|
|
{
|
|
{ "vsubp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vsubs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5D */
|
|
{
|
|
{ "vminp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
|
|
{ "vmins%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5E */
|
|
{
|
|
{ "vdivp%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
|
|
{ "vdivs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_5F */
|
|
{
|
|
{ "vmaxp%XH", { XM, Vex, EXxh, EXxEVexS }, 0 },
|
|
{ "vmaxs%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_78 */
|
|
{
|
|
{ "vcvttp%XH2udq", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
{ "vcvttsh2usi", { Gdq, EXw, EXxEVexS }, 0 },
|
|
{ "vcvttp%XH2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_79 */
|
|
{
|
|
{ "vcvtp%XH2udq", { XM, EXxmmqh, EXxEVexR }, 0 },
|
|
{ "vcvtsh2usi", { Gdq, EXw, EXxEVexR }, 0 },
|
|
{ "vcvtp%XH2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7A */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ Bad_Opcode },
|
|
{ "vcvttp%XH2qq", { XM, EXxmmqdh, EXxEVexS }, 0 },
|
|
{ VEX_W_TABLE (EVEX_W_MAP5_7A_P_3) },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7B */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vcvtusi2sh{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
|
|
{ "vcvtp%XH2qq", { XM, EXxmmqdh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7C */
|
|
{
|
|
{ "vcvttp%XH2uw", { XM, EXxh, EXxEVexS }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vcvttp%XH2w", { XM, EXxh, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP5_7D */
|
|
{
|
|
{ "vcvtp%XH2uw", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtp%XH2w", { XM, EXxh, EXxEVexR }, 0 },
|
|
{ "vcvtuw2p%XH", { XM, EXxh, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_13 */
|
|
{
|
|
{ "vcvts%XH2ss", { XMScalar, VexScalar, EXw, EXxEVexS }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vcvtp%XH2psx", { XM, EXxmmqh, EXxEVexS }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_56 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmaddcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_57 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmaddcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_D6 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmulcp%XH", { { DistinctDest_Fixup, 0 }, Vex, EXx, EXxEVexR }, 0 },
|
|
},
|
|
/* PREFIX_EVEX_MAP6_D7 */
|
|
{
|
|
{ Bad_Opcode },
|
|
{ "vfmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
{ Bad_Opcode },
|
|
{ "vfcmulcs%XH", { { DistinctDest_Fixup, scalar_mode }, VexScalar, EXd, EXxEVexR }, 0 },
|
|
},
|