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binutils-gdb/opcodes
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Tamar Christina 780f601cf3 AArch64: Replace C initializers with memset 
Clang doesn't accept {0} as a valid C struct initializer under their implementation
of -Wmissing-field-initializers.  This makes using C initializers a bit tricky.

Instead I'm changing the code to use memset instead, which at least GCC inlines and
generates the same code for.  This also seems to be the idiom used in binutils for
most targets.

opcodes/

	* aarch64-opc.c (verify_constraints): Use memset instead of {0}.
2018-10-08 13:42:37 +01:00
..
po
.gitignore
aarch64-asm-2.c
aarch64-asm.c AArch64: Constraint disassembler and assembler changes. 2018-10-03 18:51:58 +01:00
aarch64-asm.h
aarch64-dis-2.c
aarch64-dis.c AArch64: Constraint disassembler and assembler changes. 2018-10-03 18:51:58 +01:00
aarch64-dis.h
aarch64-gen.c
aarch64-opc-2.c
aarch64-opc.c AArch64: Replace C initializers with memset 2018-10-08 13:42:37 +01:00
aarch64-opc.h AArch64: Add SVE constraints verifier. 2018-10-03 18:49:37 +01:00
aarch64-tbl.h AArch64: Mark sve instructions that require MOVPRFX constraints 2018-10-03 18:24:17 +01:00
aclocal.m4 csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
alpha-dis.c
alpha-opc.c
arc-dis.c
arc-dis.h
arc-ext-tbl.h
arc-ext.c
arc-ext.h
arc-fxi.h
arc-nps400-tbl.h ARC: Fix build errors with large constants and C89 2018-09-20 15:49:00 +01:00
arc-opc.c
arc-regs.h
arc-tbl.h
arm-dis.c [Arm, 2/3] Add instruction SB for AArch32 2018-10-05 11:31:19 +01:00
avr-dis.c
bfin-dis.c
cgen-asm.c
cgen-asm.in
cgen-bitset.c
cgen-dis.c
cgen-dis.in
cgen-ibld.in
cgen-opc.c
cgen.sh
ChangeLog AArch64: Replace C initializers with memset 2018-10-08 13:42:37 +01:00
ChangeLog-0001
ChangeLog-0203
ChangeLog-2004
ChangeLog-2005
ChangeLog-2006
ChangeLog-2007
ChangeLog-2008
ChangeLog-2009
ChangeLog-2010
ChangeLog-2011
ChangeLog-2012
ChangeLog-2013
ChangeLog-2014
ChangeLog-2015
ChangeLog-2016
ChangeLog-2017
ChangeLog-9297
ChangeLog-9899
config.in
configure csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
configure.ac csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
configure.com
cr16-dis.c
cr16-opc.c
cris-dis.c
cris-opc.c
crx-dis.c
crx-opc.c
csky-dis.c
csky-opc.h csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
d10v-dis.c
d10v-opc.c
d30v-dis.c
d30v-opc.c
dep-in.sed
dis-buf.c
dis-init.c
disassemble.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
disassemble.h
dlx-dis.c
epiphany-asm.c
epiphany-desc.c
epiphany-desc.h
epiphany-dis.c
epiphany-ibld.c
epiphany-opc.c
epiphany-opc.h
fr30-asm.c
fr30-desc.c
fr30-desc.h
fr30-dis.c
fr30-ibld.c
fr30-opc.c
fr30-opc.h
frv-asm.c
frv-desc.c
frv-desc.h
frv-dis.c
frv-ibld.c
frv-opc.c
frv-opc.h
ft32-dis.c
ft32-opc.c
h8300-dis.c
hppa-dis.c
i386-dis-evex.h x86: Set EVex=2 on EVEX.128 only vmovd and vmovq 2018-09-17 09:33:35 -07:00
i386-dis.c x86: Add Intel ENCLV to assembler and disassembler 2018-10-05 11:56:42 -07:00
i386-gen.c
i386-init.h
i386-opc.c
i386-opc.h x86: Support VEX/EVEX WIG encoding 2018-09-14 12:20:10 -07:00
i386-opc.tbl x86: Add Intel ENCLV to assembler and disassembler 2018-10-05 11:56:42 -07:00
i386-reg.tbl
i386-tbl.h x86: Add Intel ENCLV to assembler and disassembler 2018-10-05 11:56:42 -07:00
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-ic.tbl
ia64-opc-a.c
ia64-opc-b.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc-i.c
ia64-opc-m.c
ia64-opc-x.c
ia64-opc.c
ia64-opc.h
ia64-raw.tbl
ia64-war.tbl
ia64-waw.tbl
ip2k-asm.c
ip2k-desc.c
ip2k-desc.h
ip2k-dis.c
ip2k-ibld.c
ip2k-opc.c
ip2k-opc.h
iq2000-asm.c
iq2000-desc.c
iq2000-desc.h
iq2000-dis.c
iq2000-ibld.c
iq2000-opc.c
iq2000-opc.h
lm32-asm.c
lm32-desc.c
lm32-desc.h
lm32-dis.c
lm32-ibld.c
lm32-opc.c
lm32-opc.h
lm32-opinst.c
m32c-asm.c
m32c-desc.c
m32c-desc.h
m32c-dis.c
m32c-ibld.c
m32c-opc.c
m32c-opc.h
m32r-asm.c
m32r-desc.c
m32r-desc.h
m32r-dis.c
m32r-ibld.c
m32r-opc.c
m32r-opc.h
m32r-opinst.c
m68hc11-dis.c
m68hc11-opc.c
m68k-dis.c
m68k-opc.c
m10200-dis.c
m10200-opc.c
m10300-dis.c
m10300-opc.c
MAINTAINERS
Makefile.am csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
Makefile.in csky-opc.h: Initialize fields of last array elements 2018-09-21 10:27:49 -04:00
makefile.vms
mcore-dis.c
mcore-opc.h
mep-asm.c
mep-desc.c
mep-desc.h
mep-dis.c
mep-ibld.c
mep-opc.c
mep-opc.h
metag-dis.c
microblaze-dis.c
microblaze-dis.h
microblaze-opc.h
microblaze-opcm.h
micromips-opc.c
mips16-opc.c
mips-dis.c [MIPS] Add Loongson 2K1000 proccessor support. 2018-08-29 20:55:25 +08:00
mips-formats.h
mips-opc.c [MIPS] Add Loongson 3A1000 proccessor support. 2018-08-29 20:32:30 +08:00
mmix-dis.c
mmix-opc.c
moxie-dis.c
moxie-opc.c
msp430-decode.c
msp430-decode.opc
msp430-dis.c
mt-asm.c
mt-desc.c
mt-desc.h
mt-dis.c
mt-ibld.c
mt-opc.c
mt-opc.h
nds32-asm.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-asm.h Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-dis.c Andes Technology has good news for you, we plan to update the nds32 port of binutils on upstream! 2018-09-20 13:32:58 +01:00
nds32-opc.h
nfp-dis.c
nios2-dis.c Fix incorrect extraction of signed constants in nios2 disassembler. 2018-09-23 12:31:23 -07:00
nios2-opc.c
ns32k-dis.c
opc2c.c
opintl.h
or1k-asm.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-desc.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-desc.h or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-dis.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-ibld.c or1k: Add the l.adrp insn and supporting relocations 2018-10-05 11:41:41 +09:00
or1k-opc.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-opc.h or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
or1k-opinst.c or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns 2018-10-05 11:41:42 +09:00
pdp11-dis.c
pdp11-opc.c
pj-dis.c
pj-opc.c
ppc-dis.c Use operand->extract to provide defaults for optional PowerPC operands 2018-08-21 16:05:36 +09:30
ppc-opc.c Use operand->extract to provide defaults for optional PowerPC operands 2018-08-21 16:05:36 +09:30
pru-dis.c
pru-opc.c
riscv-dis.c RISC-V: Allow instruction require more than one extension 2018-08-30 13:23:12 -07:00
riscv-opc.c RISC-V: Add fence.tso instruction 2018-10-02 08:26:32 -07:00
rl78-decode.c
rl78-decode.opc
rl78-dis.c
rx-decode.c
rx-decode.opc
rx-dis.c
s12z-dis.c Opcodes: (BRCLR / BRSET) Disassemble reserved codes instead of aborting. 2018-08-18 07:50:57 +02:00
s390-dis.c
s390-mkopc.c
s390-opc.c
s390-opc.txt
score7-dis.c
score-dis.c
score-opc.h
sh-dis.c
sh-opc.h Tidy bit twiddling 2018-08-20 09:54:20 +09:30
sparc-dis.c
sparc-opc.c sparc/leon: add support for partial write psr instruction 2018-08-29 20:52:28 +02:00
spu-dis.c
spu-opc.c
stamp-h.in
sysdep.h
tic4x-dis.c
tic6x-dis.c
tic30-dis.c
tic54x-dis.c
tic54x-opc.c
tic80-dis.c
tic80-opc.c
tilegx-dis.c
tilegx-opc.c
tilepro-dis.c
tilepro-opc.c
v850-dis.c
v850-opc.c
vax-dis.c
visium-dis.c
visium-opc.c
wasm32-dis.c
xc16x-asm.c
xc16x-desc.c
xc16x-desc.h
xc16x-dis.c
xc16x-ibld.c
xc16x-opc.c
xc16x-opc.h
xgate-dis.c
xgate-opc.c
xstormy16-asm.c
xstormy16-desc.c
xstormy16-desc.h
xstormy16-dis.c
xstormy16-ibld.c
xstormy16-opc.c
xstormy16-opc.h
xtensa-dis.c
z8k-dis.c
z8k-opc.h
z8kgen.c
z80-dis.c