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* cpustate.c (aarch64_get_FP_half): New function. Read a vector register as a half precision floating point number. (aarch64_set_FP_half): New function. Similar, but for setting a half precision register. (aarch64_get_thread_id): New function. Returns the value of the CPU's TPIDR register. (aarch64_get_FPCR): New function. Returns the value of the CPU's floating point control register. (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR register. * cpustate.h: Add prototypes for new functions. * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. * memory.c: Use unaligned core access functions for all memory reads and writes. * simulator.c (HALT_NYI): Generate an error message if tracing will not tell the user why the simulator is halting. (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. (INSTR): New time-saver macro. (fldrb_abs): New function. Loads an 8-bit value using a scaled offset. (fldrh_abs): New function. Likewise for 16-bit values. (do_vec_SSHL): Allow for negative shift values. (do_vec_USHL): Likewise. (do_vec_SHL): Correct computation of shift amount. (do_vec_SSHR_USHR): Correct decision of signed vs unsigned shifts and computation of shift value. (clz): New function. Counts leading zero bits. (do_vec_CLZ): New function. Implements CLZ (vector). (do_vec_MOV_element): Call do_vec_CLZ. (dexSimpleFPCondCompare): Implement. (do_FCVT_half_to_single): New function. Implements one of the FCVT operations. (do_FCVT_half_to_double): New function. Likewise. (do_FCVT_single_to_half): New function. Likewise. (do_FCVT_double_to_half): New function. Likewise. (dexSimpleFPDataProc1Source): Call new FCVT functions. (do_scalar_SHL): Handle negative shifts. (do_scalar_shift): Handle SSHR. (do_scalar_USHL): New function. (do_double_add): Simplify to just performing a double precision add operation. Move remaining code into... (do_scalar_vec): ... New function. (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs functions. (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR registers. (system_set): New function. (do_MSR_immediate): New function. Stub for now. (do_MSR_reg): New function. Likewise. Partially implements MSR instruction. (do_SYS): New function. Stub for now, (dexSystem): Call new functions.
71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/* sim-main.h -- Interface with sim/common.
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Copyright (C) 2015-2016 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef _SIM_MAIN_H
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#define _SIM_MAIN_H
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#include "sim-basics.h"
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#include "sim-types.h"
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#include "sim-base.h"
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#include "sim-base.h"
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#include "sim-io.h"
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#include "cpustate.h"
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/* A per-core state structure. */
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struct _sim_cpu
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{
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GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
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FRegister fr[32];
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uint64_t pc;
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uint32_t CPSR;
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uint32_t FPSR; /* Floating point Status register. */
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uint32_t FPCR; /* Floating point Control register. */
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uint64_t nextpc;
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uint32_t instr;
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uint64_t tpidr; /* Thread pointer id. */
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sim_cpu_base base;
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};
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typedef enum
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{
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AARCH64_MIN_GR = 0,
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AARCH64_MAX_GR = 31,
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AARCH64_MIN_FR = 32,
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AARCH64_MAX_FR = 63,
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AARCH64_PC_REGNO = 64,
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AARCH64_CPSR_REGNO = 65,
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AARCH64_FPSR_REGNO = 66,
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AARCH64_MAX_REGNO = 67
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} aarch64_regno;
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/* The simulator state structure used to hold all global variables. */
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struct sim_state
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{
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sim_cpu * cpu[MAX_NR_PROCESSORS];
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sim_state_base base;
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};
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#endif /* _SIM_MAIN_H */
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