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a71d876801
The logic to decide if an input relocation for a symbol becomes a particular kind of output relocation is one of the hard to maintain parts of the bfd ld backend, since it is partially repeated across elfNN_aarch64_check_relocs (where dynamic relocations are counted per symbol and input section), elfNN_aarch64_late_size_sections (where relocation sections are sized and GOT offsets assigned), elfNN_aarch64_relocate_section (where most relocations are applied and output to a relocation section), elfNN_aarch64_finish_dynamic_symbol (where some of the GOT relocations are applied and output). The DT_RELR support adds another layer to this complexity: after the output relocation sections are sized, so all dynamic relocations are accounted (in elfNN_aarch64_late_size_sections), we scan the symbols and input relocations again to decide which ones become relative relocations that can be packed. The sizes of the relocation sections are updated accordingly. This logic must be consistent with the code that applies the relocs later so each relative relocation is emitted exactly once: either in .rela.* or packed in .relr.dyn. Sizing of .relr.dyn is done via elfNN_aarch64_size_relative_relocs that may be called repeatedly whenever the layout changes since an address change can affect the size of the packed format. Then the final content is emitted in elfNN_aarch64_finish_relative_relocs, that is called after the layout is final and before relocations are applied and emitted. These hooks are only called if DT_RELR is enabled. We only pack relative relocs that are known to be aligned in the output during .relr.dyn sizing, the potentially unaligned relative relocs are emitted normally (in .rela.*, not packed), because the format requires aligned addresses.
40 lines
1.2 KiB
Bash
40 lines
1.2 KiB
Bash
source_sh ${srcdir}/emulparams/dt-relr.sh
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ARCH=aarch64
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MACHINE=
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NOP=0x1f2003d5
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SCRIPT_NAME=elf
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ELFSIZE=64
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OUTPUT_FORMAT="elf64-littleaarch64"
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BIG_OUTPUT_FORMAT="elf64-bigaarch64"
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LITTLE_OUTPUT_FORMAT="elf64-littleaarch64"
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NO_REL_RELOCS=yes
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TEMPLATE_NAME=elf
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EXTRA_EM_FILE=aarch64elf
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GENERATE_SHLIB_SCRIPT=yes
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GENERATE_PIE_SCRIPT=yes
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MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"
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COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)"
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SEPARATE_GOTPLT=24
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IREL_IN_PLT=
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TEXT_START_ADDR=0x400000
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DATA_START_SYMBOLS='PROVIDE (__data_start = .);';
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# AArch64 does not support .s* sections.
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NO_SMALL_DATA=yes
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OTHER_BSS_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__bss_start__ = .${CREATE_SHLIB+)};"
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OTHER_BSS_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}_bss_end__ = .${CREATE_SHLIB+)}; ${CREATE_SHLIB+PROVIDE (}__bss_end__ = .${CREATE_SHLIB+)};"
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OTHER_END_SYMBOLS="${CREATE_SHLIB+PROVIDE (}__end__ = .${CREATE_SHLIB+)};"
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OTHER_SECTIONS='.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }'
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ATTRS_SECTIONS='.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }'
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# Ensure each PLT entry is aligned to a cache line.
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PLT=".plt ${RELOCATING-0} : ALIGN(16) { *(.plt)${RELOCATING+${IREL_IN_PLT+ *(.iplt)}} }"
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