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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
657 lines
13 KiB
PHP
657 lines
13 KiB
PHP
# gr28-gr31, fr31, icc3, fcc3 are used as tmps.
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# consider them call clobbered by these macros.
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.macro start
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.data
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failmsg:
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.ascii "fail\n"
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passmsg:
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.ascii "pass\n"
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.text
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.global _start
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_start:
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; enable data and insn caches in copy-back mode
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; Also enable all registers
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or_spr_immed 0xc80003c0,hsr0
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and_spr_immed 0xfffff3ff,hsr0
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; turn on psr.nem, psr.cm, psr.ef, psr.em, psr.esr,
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; disable external interrupts
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or_spr_immed 0x69f8,psr
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; If fsr exists, enable all fp_exceptions except inexact
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movsg psr,gr28
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srli gr28,28,gr28
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subicc gr28,0x2,gr0,icc3 ; is fr400?
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beq icc3,0,nofsr0
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or_spr_immed 0x3d000000,fsr0
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nofsr0:
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; Set the stack pointer
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sethi.p 0x7,sp
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setlo 0xfffc,sp ; TODO -- what's a good value for this?
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; Set the TBR address
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sethi.p 0xf,gr28
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setlo 0xf000,gr28
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movgs gr28,tbr ; TODO -- what's a good value for this?
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; Go to user mode -- causes too many problems
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;and_spr_immed 0xfffffffb,psr
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.endm
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; Set GR with another GR
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.macro set_gr_gr src targ
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addi \src,0,\targ
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.endm
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; Set GR with immediate value
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.macro set_gr_immed val reg
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.if (\val >= -32768) && (\val <= 23767)
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setlos \val,\reg
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.else
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setlo.p %lo(\val),\reg
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sethi %hi(\val),\reg
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.endif
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.endm
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.macro set_gr_limmed valh vall reg
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sethi.p \valh,\reg
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setlo \vall,\reg
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.endm
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; Set GR with address value
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.macro set_gr_addr addr reg
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sethi.p %hi(\addr),\reg
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setlo %lo(\addr),\reg
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.endm
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; Set GR with SPR
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.macro set_gr_spr src targ
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movsg \src,\targ
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.endm
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; Set GR with a value from memory
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.macro set_gr_mem addr reg
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set_gr_addr \addr,gr28
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ldi @(gr28,0),\reg
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.endm
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; Increment GR with immediate value
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.macro inc_gr_immed val reg
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.if (\val >= -2048) && (\val <= 2047)
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addi \reg,\val,\reg
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.else
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set_gr_immed \val,gr28
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add \reg,gr28,\reg
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.endif
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.endm
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; AND GR with immediate value
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.macro and_gr_immed val reg
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.if (\val >= -2048) && (\val <= 2047)
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andi \reg,\val,\reg
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.else
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set_gr_immed \val,gr28
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and \reg,gr28,\reg
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.endif
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.endm
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; OR GR with immediate value
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.macro or_gr_immed val reg
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.if (\val >= -2048) && (\val <= 2047)
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ori \reg,\val,\reg
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.else
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set_gr_immed \val,gr28
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or \reg,gr28,\reg
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.endif
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.endm
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; Set FR with another FR
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.macro set_fr_fr src targ
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fmovs \src,\targ
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.endm
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; Set FR with integer immediate value
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.macro set_fr_iimmed valh vall reg
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set_gr_limmed \valh,\vall,gr28
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movgf gr28,\reg
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.endm
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; Set FR with integer immediate value
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.macro set_fr_immed val reg
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set_gr_immed \val,gr28
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movgf gr28,\reg
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.endm
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; Set FR with a value from memory
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.macro set_fr_mem addr reg
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set_gr_addr \addr,gr28
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ldfi @(gr28,0),\reg
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.endm
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; Set double FR with another double FR
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.macro set_dfr_dfr src targ
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fmovd \src,\targ
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.endm
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; Set double FR with a value from memory
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.macro set_dfr_mem addr reg
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set_gr_addr \addr,gr28
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lddfi @(gr28,0),\reg
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.endm
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; Set CPR with immediate value
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.macro set_cpr_immed val reg
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addi sp,-4,gr28
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set_gr_immed \val,gr29
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st gr29,@(gr28,gr0)
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ldc @(gr28,gr0),\reg
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.endm
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.macro set_cpr_limmed valh vall reg
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addi sp,-4,gr28
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set_gr_limmed \valh,\vall,gr29
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st gr29,@(gr28,gr0)
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ldc @(gr28,gr0),\reg
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.endm
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; Set SPR with immediate value
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.macro set_spr_immed val reg
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set_gr_immed \val,gr28
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movgs gr28,\reg
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.endm
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.macro set_spr_limmed valh vall reg
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set_gr_limmed \valh,\vall,gr28
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movgs gr28,\reg
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.endm
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.macro set_spr_addr addr reg
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set_gr_addr \addr,gr28
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movgs gr28,\reg
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.endm
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; increment SPR with immediate value
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.macro inc_spr_immed val reg
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movsg \reg,gr28
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inc_gr_immed \val,gr28
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movgs gr28,\reg
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.endm
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; OR spr with immediate value
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.macro or_spr_immed val reg
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movsg \reg,gr28
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set_gr_immed \val,gr29
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or gr28,gr29,gr28
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movgs gr28,\reg
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.endm
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; AND spr with immediate value
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.macro and_spr_immed val reg
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movsg \reg,gr28
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set_gr_immed \val,gr29
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and gr28,gr29,gr28
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movgs gr28,\reg
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.endm
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; Set accumulator with immediate value
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.macro set_acc_immed val reg
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set_fr_immed \val,fr31
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mwtacc fr31,\reg
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.endm
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; Set accumulator guard with immediate value
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.macro set_accg_immed val reg
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set_fr_immed \val,fr31
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mwtaccg fr31,\reg
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.endm
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; Set memory with immediate value
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.macro set_mem_immed val base
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set_gr_immed \val,gr28
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sti gr28,@(\base,0)
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.endm
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.macro set_mem_limmed valh vall base
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set_gr_limmed \valh,\vall,gr28
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sti gr28,@(\base,0)
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.endm
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; Set memory with GR value
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.macro set_mem_gr reg addr
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set_gr_addr \addr,gr28
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sti \reg,@(gr28,0)
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.endm
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; Test the value of a general register against another general register
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.macro test_gr_gr reg1 reg2
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subcc \reg1,\reg2,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Test the value of an immediate against a general register
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.macro test_gr_immed val reg
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.if (\val >= -512) && (\val <= 511)
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subicc \reg,\val,gr0,icc3
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.else
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set_gr_immed \val,gr28
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subcc \reg,gr28,gr0,icc3
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.endif
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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.macro test_gr_limmed valh vall reg
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set_gr_limmed \valh,\vall,gr28
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subcc \reg,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Test the value of an floating register against an integer immediate
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.macro test_fr_limmed valh vall reg
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movfg \reg,gr29
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set_gr_limmed \valh,\vall,gr28
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subcc gr29,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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.macro test_fr_iimmed val reg
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movfg \reg,gr29
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set_gr_immed \val,gr28
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subcc gr29,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Test the value of a floating register against another floating point register
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.macro test_fr_fr reg1 reg2
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fcmps \reg1,\reg2,fcc3
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fbeq fcc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Test the value of a double floating register against another
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; double floating point register
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.macro test_dfr_dfr reg1 reg2
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fcmpd \reg1,\reg2,fcc3
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fbeq fcc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Test the value of a special purpose register against an integer immediate
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.macro test_spr_immed val reg
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movsg \reg,gr29
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set_gr_immed \val,gr28
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subcc gr29,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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.macro test_spr_limmed valh vall reg
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movsg \reg,gr29
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set_gr_limmed \valh,\vall,gr28
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subcc gr29,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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.macro test_spr_gr spr gr
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movsg \spr,gr28
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test_gr_gr \gr,gr28
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.endm
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.macro test_spr_addr addr reg
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movsg \reg,gr29
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set_gr_addr \addr,gr28
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test_gr_gr gr28,gr29
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.endm
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; Test spr bits masked and shifted against the given value
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.macro test_spr_bits mask,shift,val,reg
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movsg \reg,gr28
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set_gr_immed \mask,gr29
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and gr28,gr29,gr28
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srli gr28,\shift,gr29
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test_gr_immed \val,gr29
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.endm
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; Test the value of an accumulator against an integer immediate
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.macro test_acc_immed val reg
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mrdacc \reg,fr31
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test_fr_iimmed \val,fr31
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.endm
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; Test the value of an accumulator against an integer immediate
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.macro test_acc_limmed valh vall reg
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mrdacc \reg,fr31
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test_fr_limmed \valh,\vall,fr31
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.endm
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; Test the value of an accumulator guard against an integer immediate
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.macro test_accg_immed val reg
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mrdaccg \reg,fr31
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test_fr_iimmed \val,fr31
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.endm
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; Test CPR agains an immediate value
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.macro test_cpr_limmed valh vall reg
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addi sp,-4,gr31
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stc \reg,@(gr31,gr0)
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test_mem_limmed \valh,\vall,gr31
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.endm
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; Test the value of an immediate against memory
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.macro test_mem_immed val base
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ldi @(\base,0),gr29
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.if (\val >= -512) && (\val <= 511)
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subicc gr29,\val,gr0,icc3
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.else
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set_gr_immed \val,gr28
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subcc gr29,gr28,gr0,icc3
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.endif
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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.macro test_mem_limmed valh vall base
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ldi @(\base,0),gr29
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set_gr_limmed \valh,\vall,gr28
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subcc gr29,gr28,gr0,icc3
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beq icc3,0,test_gr\@
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fail
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test_gr\@:
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.endm
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; Set an integer condition code
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.macro set_icc mask iccno
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set_gr_immed 4,gr29
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smuli gr29,\iccno,gr30
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addi gr31,16,gr31
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set_gr_immed 0xf,gr28
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sll gr28,gr31,gr28
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not gr28,gr28
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movsg ccr,gr29
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and gr28,gr29,gr29
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set_gr_immed \mask,gr28
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sll gr28,gr31,gr28
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or gr28,gr29,gr29
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movgs gr29,ccr
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.endm
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; started here
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; Test the condition codes
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.macro test_icc N Z V C iccno
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.if (\N == 1)
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bp \iccno,0,fail\@
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.else
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bn \iccno,0,fail\@
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.endif
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.if (\Z == 1)
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bne \iccno,0,fail\@
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.else
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beq \iccno,0,fail\@
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.endif
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.if (\V == 1)
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bnv \iccno,0,fail\@
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.else
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bv \iccno,0,fail\@
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.endif
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.if (\C == 1)
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bnc \iccno,0,fail\@
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.else
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bc \iccno,0,fail\@
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.endif
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bra test_cc\@
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fail\@:
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fail
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test_cc\@:
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.endm
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; Set an floating point condition code
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.macro set_fcc mask fccno
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set_gr_immed 4,gr29
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smuli gr29,\fccno,gr30
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set_gr_immed 0xf,gr28
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sll gr28,gr31,gr28
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not gr28,gr28
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movsg ccr,gr29
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and gr28,gr29,gr29
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set_gr_immed \mask,gr28
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sll gr28,gr31,gr28
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or gr28,gr29,gr29
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movgs gr29,ccr
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.endm
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; Test the condition codes
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.macro test_fcc val fccno
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set_gr_immed 4,gr29
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smuli gr29,\fccno,gr30
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movsg ccr,gr29
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srl gr29,gr31,gr29
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andi gr29,0xf,gr29
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test_gr_immed \val,gr29
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.endm
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; Set PSR.ET
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.macro set_psr_et val
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movsg psr,gr28
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.if (\val == 1)
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ori gr28,1,gr28 ; Turn on SPR.ET
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.else
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andi gr28,0xfffffffe,gr28 ; Turn off SPR.ET
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.endif
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movgs gr28,psr
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.endm
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; Floating point constants
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.macro float_constants
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f0: .float 0.0
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f1: .float 1.0
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f2: .float 2.0
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f3: .float 3.0
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f6: .float 6.0
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f9: .float 9.0
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fn0: .float -0.0
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fn1: .float -1.0
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finf: .long 0x7f800000
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fninf: .long 0xff800000
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fmax: .long 0x7f7fffff
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fmin: .long 0xff7fffff
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feps: .long 0x00400000
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fneps: .long 0x80400000
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fnan1: .long 0x7fc00000
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fnan2: .long 0x7f800001
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.endm
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.macro double_constants
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d0: .double 0.0
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d1: .double 1.0
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d2: .double 2.0
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d3: .double 3.0
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d6: .double 6.0
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d9: .double 9.0
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dn0: .double -0.0
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dn1: .double -1.0
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dinf: .long 0x7ff00000
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.long 0x00000000
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dninf: .long 0xfff00000
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.long 0x00000000
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dmax: .long 0x7fefffff
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.long 0xffffffff
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dmin: .long 0xffefffff
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.long 0xffffffff
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deps: .long 0x00080000
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.long 0x00000000
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dneps: .long 0x80080000
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.long 0x00000000
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dnan1: .long 0x7ff80000
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.long 0x00000000
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dnan2: .long 0x7ff00000
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.long 0x00000001
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.endm
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; Load floating point constants
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.macro load_float_constants
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set_fr_mem fninf,fr0
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set_fr_mem fmin,fr4
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set_fr_mem fn1,fr8
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set_fr_mem fneps,fr12
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set_fr_mem fn0,fr16
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set_fr_mem f0,fr20
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set_fr_mem feps,fr24
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set_fr_mem f1,fr28
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set_fr_mem f2,fr32
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set_fr_mem f3,fr36
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set_fr_mem f6,fr40
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set_fr_mem f9,fr44
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set_fr_mem fmax,fr48
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set_fr_mem finf,fr52
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set_fr_mem fnan1,fr56
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set_fr_mem fnan2,fr60
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.endm
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.macro load_float_constants1
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set_fr_mem fninf,fr1
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set_fr_mem fmin,fr5
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set_fr_mem fn1,fr9
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set_fr_mem fneps,fr13
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set_fr_mem fn0,fr17
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|
set_fr_mem f0,fr21
|
|
set_fr_mem feps,fr25
|
|
set_fr_mem f1,fr29
|
|
set_fr_mem f2,fr33
|
|
set_fr_mem f3,fr37
|
|
set_fr_mem f6,fr41
|
|
set_fr_mem f9,fr45
|
|
set_fr_mem fmax,fr49
|
|
set_fr_mem finf,fr53
|
|
set_fr_mem fnan1,fr57
|
|
set_fr_mem fnan2,fr61
|
|
.endm
|
|
|
|
.macro load_float_constants2
|
|
set_fr_mem fninf,fr2
|
|
set_fr_mem fmin,fr6
|
|
set_fr_mem fn1,fr10
|
|
set_fr_mem fneps,fr14
|
|
set_fr_mem fn0,fr18
|
|
set_fr_mem f0,fr22
|
|
set_fr_mem feps,fr26
|
|
set_fr_mem f1,fr30
|
|
set_fr_mem f2,fr34
|
|
set_fr_mem f3,fr38
|
|
set_fr_mem f6,fr42
|
|
set_fr_mem f9,fr46
|
|
set_fr_mem fmax,fr50
|
|
set_fr_mem finf,fr54
|
|
set_fr_mem fnan1,fr58
|
|
set_fr_mem fnan2,fr62
|
|
.endm
|
|
|
|
.macro load_float_constants3
|
|
set_fr_mem fninf,fr3
|
|
set_fr_mem fmin,fr7
|
|
set_fr_mem fn1,fr11
|
|
set_fr_mem fneps,fr15
|
|
set_fr_mem fn0,fr19
|
|
set_fr_mem f0,fr23
|
|
set_fr_mem feps,fr27
|
|
set_fr_mem f1,fr31
|
|
set_fr_mem f2,fr35
|
|
set_fr_mem f3,fr39
|
|
set_fr_mem f6,fr43
|
|
set_fr_mem f9,fr47
|
|
set_fr_mem fmax,fr51
|
|
set_fr_mem finf,fr55
|
|
set_fr_mem fnan1,fr59
|
|
set_fr_mem fnan2,fr63
|
|
.endm
|
|
|
|
.macro load_double_constants
|
|
set_dfr_mem dninf,fr0
|
|
set_dfr_mem dmin,fr4
|
|
set_dfr_mem dn1,fr8
|
|
set_dfr_mem dneps,fr12
|
|
set_dfr_mem dn0,fr16
|
|
set_dfr_mem d0,fr20
|
|
set_dfr_mem deps,fr24
|
|
set_dfr_mem d1,fr28
|
|
set_dfr_mem d2,fr32
|
|
set_dfr_mem d3,fr36
|
|
set_dfr_mem d6,fr40
|
|
set_dfr_mem d9,fr44
|
|
set_dfr_mem dmax,fr48
|
|
set_dfr_mem dinf,fr52
|
|
set_dfr_mem dnan1,fr56
|
|
set_dfr_mem dnan2,fr60
|
|
.endm
|
|
|
|
; Lock the insn cache at the given address
|
|
.macro lock_insn_cache address
|
|
icpl \address,gr0,1
|
|
.endm
|
|
|
|
; Lock the data cache at the given address
|
|
.macro lock_data_cache address
|
|
dcpl \address,gr0,1
|
|
.endm
|
|
|
|
; Invalidate the data cache at the given address
|
|
.macro invalidate_data_cache address
|
|
dci @(\address,gr0)
|
|
.endm
|
|
|
|
; Flush the data cache at the given address
|
|
.macro flush_data_cache address
|
|
dcf @(\address,gr0)
|
|
.endm
|
|
|
|
; Write a bctrlr 0,0 insn at the address contained in the given register
|
|
.macro set_bctrlr_0_0 address
|
|
set_mem_immed 0x80382000,\address ; bctrlr 0,0
|
|
flush_data_cache \address
|
|
.endm
|
|
|
|
; Exit with return code
|
|
.macro exit rc
|
|
setlos #1,gr7
|
|
set_gr_immed \rc,gr8
|
|
tira gr0,#0
|
|
.endm
|
|
|
|
; Pass the test case
|
|
.macro pass
|
|
pass\@:
|
|
setlos.p #5,gr10
|
|
setlos #1,gr8
|
|
setlos #5,gr7
|
|
set_gr_addr passmsg,gr9
|
|
tira gr0,#0
|
|
exit #0
|
|
.endm
|
|
|
|
; Fail the testcase
|
|
.macro fail
|
|
fail\@:
|
|
setlos.p #5,gr10
|
|
setlos #1,gr8
|
|
setlos #5,gr7
|
|
set_gr_addr failmsg,gr9
|
|
tira gr0,#0
|
|
exit #1
|
|
.endm
|