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1368b914e9
Now that all port tests live under testsuite/sim/*/, and none live in testsuite/ directly, flatten the structure by moving all of the dirs under testsuite/sim/ to testsuite/ directly. We need to stop passing --tool to dejagnu so that it searches all dirs and not just ones that start with "sim". Since we have no other dirs in this tree, and no plans to add any, should be fine.
355 lines
9.7 KiB
Plaintext
355 lines
9.7 KiB
Plaintext
# frv testcase for smsss $GRi,$GRj
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# mach: fr405 fr450
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.include "../testutils.inc"
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start
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.global smsss
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smsss1:
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; Positive operands
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 7,iacc0l
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smsss gr7,gr8
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test_gr_immed 3,gr7
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test_gr_immed 2,gr8
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test_spr_immed 1,iacc0l ; result 7-3*2
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test_spr_immed 0,iacc0h
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smsss2:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 3,iacc0l
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smsss gr7,gr8
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test_gr_immed 1,gr7
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test_gr_immed 2,gr8
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test_spr_immed 1,iacc0l ; result 3-1*2
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test_spr_immed 0,iacc0h
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smsss3:
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set_gr_immed 2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 3,iacc0l
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smsss gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed 2,gr7
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test_spr_immed 1,iacc0l ; result 3-2*1
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test_spr_immed 0,iacc0h
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smsss4:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed 2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed 0,gr7
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test_spr_immed 1,iacc0l ; result 1-0*2
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test_spr_immed 0,iacc0h
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smsss5:
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set_gr_immed 2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed 2,gr7
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test_spr_immed 1,iacc0l ; result 1-2*0
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test_spr_immed 0,iacc0h
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smsss6:
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set_gr_limmed 0x3fff,0xffff,gr7 ; 31 bit result
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set_gr_immed 2,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -1,iacc0l
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smsss gr7,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x3fff,0xffff,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; -1-3fffffff*2
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test_spr_immed -1,iacc0h
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smsss7:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed 2,gr8
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set_spr_immed -1,iacc0h
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set_spr_limmed 0x8000,0x0001,iacc0l
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smsss gr7,gr8
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test_gr_immed 2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_immed 1,iacc0l ; ffffffff80000001-40000000*2
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test_spr_immed -1,iacc0h
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smsss8:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed 4,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed 4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_immed 1,iacc0l ; ffffffff00000001-40000000*4
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test_spr_immed -2,iacc0h
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smsss9:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max positive result
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0x7fff,0xffff,iacc0h
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set_spr_immed -1,iacc0l
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smsss gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xfffe,iacc0l ; 7fffffffffffffff-7fffffff*7fffffff
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test_spr_limmed 0x4000,0x0000,iacc0h
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smsss10:
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; Mixed operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed 2,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -5,iacc0l
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smsss gr7,gr8
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test_gr_immed 2,gr8
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test_gr_immed -3,gr7
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test_spr_immed 1,iacc0l ; -5-(-3*2)
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test_spr_immed 0,iacc0h
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smsss11:
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set_gr_immed 3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -5,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 3,gr7
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test_spr_immed 1,iacc0l ; -5-(3*-2)
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test_spr_immed 0,iacc0h
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smsss12:
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set_gr_immed 1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -1,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 1,gr7
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test_spr_immed 1,iacc0l ; -1-(1*-2)
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test_spr_immed 0,iacc0h
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smsss13:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed 1,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -1,iacc0l
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smsss gr7,gr8
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test_gr_immed 1,gr8
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test_gr_immed -2,gr7
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test_spr_immed 1,iacc0l ; -1-(-2*1)
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test_spr_immed 0,iacc0h
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smsss14:
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set_gr_immed 0,gr7 ; multiply by 0
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed 0,gr7
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test_spr_immed 1,iacc0l ; 1-(0*-2)
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test_spr_immed 0,iacc0h
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smsss15:
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set_gr_immed -2,gr7 ; multiply by 0
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set_gr_immed 0,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed -2,gr7
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test_spr_immed 1,iacc0l ; 1-(-2*0)
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test_spr_immed 0,iacc0h
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smsss16:
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set_gr_limmed 0x2000,0x0000,gr7 ; 31 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_limmed 0x3fff,0xffff,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x2000,0x0000,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l
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test_spr_immed 0,iacc0h ; 3fffffff-20000001*-2
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smsss17:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x8000,0x0001,iacc0l ; 1-40000000*-2
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test_spr_immed 0,iacc0h
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smsss18:
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set_gr_limmed 0x4000,0x0000,gr7 ; 32 bit result
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set_gr_immed -2,gr8
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set_spr_immed -1,iacc0h
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set_spr_immed -1,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l
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test_spr_immed 0,iacc0h ; -1-40000000*-2
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smsss19:
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set_gr_limmed 0x4000,0x0000,gr7 ; 33 bit result
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set_gr_immed -4,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_immed -4,gr8
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test_gr_limmed 0x4000,0x0000,gr7
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test_spr_immed 1,iacc0l ; 200000001-(40000000*-4)
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test_spr_immed 1,iacc0h
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smsss20:
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set_gr_limmed 0x7fff,0xffff,gr7 ; max negative result
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0xbfff,0xffff,iacc0h
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set_spr_limmed 0x0000,0x0001,iacc0l
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smsss gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_immed 0,iacc0l ; bfffffff00000001-(7fffffff*7fffffff)
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test_spr_limmed 0x8000,0x0000,iacc0h
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smsss21:
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; Negative operands
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set_gr_immed -3,gr7 ; multiply small numbers
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 7,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -3,gr7
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test_spr_immed 1,iacc0l ; 7-(-3*-2)
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test_spr_immed 0,iacc0h
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smsss22:
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set_gr_immed -1,gr7 ; multiply by 1
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set_gr_immed -2,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 3,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -1,gr7
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test_spr_immed 1,iacc0l ; 3-(-1*-2)
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test_spr_immed 0,iacc0h
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smsss23:
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set_gr_immed -2,gr7 ; multiply by 1
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set_gr_immed -1,gr8
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set_spr_immed 0,iacc0h
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set_spr_immed 3,iacc0l
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smsss gr7,gr8
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test_gr_immed -1,gr8
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test_gr_immed -2,gr7
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test_spr_immed 1,iacc0l ; 3-(-2*-1)
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test_spr_immed 0,iacc0h
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smsss24:
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set_gr_immed -32768,gr7 ; 31 bit result
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set_gr_immed -32768,gr8
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set_spr_immed 0,iacc0h
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set_spr_limmed 0xbfff,0xffff,iacc0l
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smsss gr7,gr8
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test_gr_immed -32768,gr8
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test_gr_immed -32768,gr7
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test_spr_limmed 0x7fff,0xffff,iacc0l ; 7ffffffb-(-2*-2)
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test_spr_immed 0,iacc0h
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smsss25:
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set_gr_immed 0xffff,gr7 ; 32 bit result
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set_gr_immed 0xffff,gr8
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set_spr_immed 1,iacc0h
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set_spr_limmed 0xfffe,0x0000,iacc0l
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smsss gr7,gr8
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test_gr_immed 0xffff,gr8
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test_gr_immed 0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 1fffe0000-ffff*ffff
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test_spr_immed 0,iacc0h
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smsss26:
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set_gr_limmed 0x0001,0x0000,gr7 ; 33 bit result
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set_gr_limmed 0x0001,0x0000,gr8
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set_spr_immed 2,iacc0h
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set_spr_immed 1,iacc0l
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smsss gr7,gr8
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test_gr_limmed 0x0001,0x0000,gr8
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test_gr_limmed 0x0001,0x0000,gr7
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test_spr_immed 1,iacc0l ; 0x200000001-0x10000*0x10000
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test_spr_immed 1,iacc0h
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smsss27:
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set_gr_immed -2,gr7 ; almost max positive result
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set_gr_immed -2,gr8
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set_spr_limmed 0x7fff,0xffff,iacc0h
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set_spr_limmed 0xffff,0xffff,iacc0l
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smsss gr7,gr8
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test_gr_immed -2,gr8
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test_gr_immed -2,gr7
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test_spr_limmed 0xffff,0xfffb,iacc0l ; maxpos - (-2*-2)
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test_spr_limmed 0x7fff,0xffff,iacc0h
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smsss28:
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set_gr_immed 0,gr7 ; max positive result
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set_gr_immed 0,gr8
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set_spr_limmed 0x7fff,0xffff,iacc0h
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set_spr_limmed 0xffff,0xffff,iacc0l
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smsss gr7,gr8
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test_gr_immed 0,gr8
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test_gr_immed 0,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; maxpos-(0*0)
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test_spr_limmed 0x7fff,0xffff,iacc0h
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smsss29:
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set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (pos)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0x4000,0x0000,iacc0h
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set_spr_limmed 0x7fff,0xffff,iacc0l
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smsss gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 400000007fffffff -
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
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smsss30:
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set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (pos)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0x4000,0x0000,iacc0h
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set_spr_limmed 0x8000,0x0000,iacc0l
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smsss gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 4000000080000000 -
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 0x80000000*0x7fffffff
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smsss31:
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set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (pos)
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set_gr_limmed 0x8000,0x0000,gr8
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set_spr_limmed 0xffff,0xffff,iacc0l
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set_spr_limmed 0x7fff,0xffff,iacc0h
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smsss gr7,gr8
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test_gr_limmed 0x8000,0x0000,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0xffff,0xffff,iacc0l ; 7fffffffffffffff -
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test_spr_limmed 0x7fff,0xffff,iacc0h ; 80000000*80000000
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smsss32:
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set_gr_limmed 0x7fff,0xffff,gr7 ; not quite overflow (neg)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_immed 1,iacc0l
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set_spr_limmed 0xbfff,0xffff,iacc0h
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smsss gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; bfffffff00000001 -
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test_spr_limmed 0x8000,0x0000,iacc0h ; 0x7fffffff*0x7fffffff
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smsss33:
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set_gr_limmed 0x7fff,0xffff,gr7 ; just barely overflow (neg)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_immed 0,iacc0l
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set_spr_limmed 0xbfff,0xffff,iacc0h
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smsss gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; 7fffffff*7fffffff+
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test_spr_limmed 0x8000,0x0000,iacc0h ; bfffffff7fffffff
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smsss34:
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set_gr_limmed 0x7fff,0xffff,gr7 ; maximum overflow (neg)
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set_gr_limmed 0x7fff,0xffff,gr8
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set_spr_limmed 0x0000,0x0000,iacc0l
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set_spr_limmed 0x8000,0x0000,iacc0h
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smsss gr7,gr8
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test_gr_limmed 0x7fff,0xffff,gr8
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test_gr_limmed 0x7fff,0xffff,gr7
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test_spr_limmed 0x0000,0x0000,iacc0l ; 8000000000000000-
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test_spr_limmed 0x8000,0x0000,iacc0h ; 7fffffff*7fffffff+
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pass
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